diff options
| author | Anuj Phogat <[email protected]> | 2018-10-02 04:28:10 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-11-26 15:11:36 -0800 |
| commit | 3282c7be899f34cd6d2fe695976383c949e1c6c2 (patch) | |
| tree | d457503522d29537725227ec19951dbc682ae91d /src/intel/common/gen_l3_config.c | |
| parent | c0c533767e2a97cb88dcff56f83ae5472e6592cb (diff) | |
i965/icl: Fix L3 configurations
Use L3 configuration specified in h/w specification.
V2: Drop configs which do under allocation of l3 cache.
Bump up the comment above table.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'src/intel/common/gen_l3_config.c')
| -rw-r--r-- | src/intel/common/gen_l3_config.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c index b977c6ab136..32264394fb6 100644 --- a/src/intel/common/gen_l3_config.c +++ b/src/intel/common/gen_l3_config.c @@ -134,15 +134,15 @@ static const struct gen_l3_config cnl_l3_configs[] = { /** * ICL validated L3 configurations. \sa icl_l3_configs. + * Zeroth entry in below table has been commented out intentionally + * due to known issues with this configuration. Many other entries + * suggested by h/w specification aren't added here because they + * do under allocation of L3 cache with below partitioning. */ static const struct gen_l3_config icl_l3_configs[] = { /* SLM URB ALL DC RO IS C T */ - {{ 0, 64, 64, 0, 0, 0, 0, 0 }}, - {{ 0, 64, 0, 16, 48, 0, 0, 0 }}, - {{ 0, 48, 0, 16, 64, 0, 0, 0 }}, - {{ 0, 32, 0, 0, 96, 0, 0, 0 }}, - {{ 0, 32, 96, 0, 0, 0, 0, 0 }}, - {{ 0, 32, 0, 16, 80, 0, 0, 0 }}, + /*{{ 0, 16, 80, 0, 0, 0, 0, 0 }},*/ + {{ 0, 32, 64, 0, 0, 0, 0, 0 }}, {{ 0 }} }; |