summaryrefslogtreecommitdiffstats
path: root/src/intel/blorp
diff options
context:
space:
mode:
authorRafael Antognolli <[email protected]>2019-11-13 14:30:57 -0800
committerRafael Antognolli <[email protected]>2019-11-19 21:43:09 +0000
commitdadb6ebbd1e4575b7f8ee14dc5b9447091c2ce9e (patch)
tree2706870a11cd301c03105a572001281194d6b5d9 /src/intel/blorp
parentd2cf3cad917758b64f700bebe50406fc81337044 (diff)
intel: Add workaround for stencil state.
Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]>
Diffstat (limited to 'src/intel/blorp')
-rw-r--r--src/intel/blorp/blorp_genX_exec.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index 3c18423ad3b..9f75efe012d 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1624,6 +1624,20 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch,
}
isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info);
+
+#if GEN_GEN >= 12
+ /* GEN:BUG:1408224581
+ *
+ * Workaround: Gen12LP Astep only An additional pipe control with
+ * post-sync = store dword operation would be required.( w/a is to
+ * have an additional pipe control after the stencil state whenever
+ * the surface state bits of this state is changing).
+ */
+ blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
+ pc.PostSyncOperation = WriteImmediateData;
+ pc.Address = blorp_get_workaround_page(batch);
+ }
+#endif
}
#if GEN_GEN >= 8