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authorJason Ekstrand <[email protected]>2018-05-25 12:27:17 -0700
committerJason Ekstrand <[email protected]>2018-05-25 14:01:44 -0700
commitae514ca695a599cdd0b7c22f48fd4d721671b0cb (patch)
tree4e4925626076b41769ea15905ba2771754e4424a /src/intel/blorp/blorp.c
parent2f65c67043529f8f7fca8514f88251f935e61c2c (diff)
intel/blorp: Support blits and clears on surfaces with offsets
For certain EGLImage cases, we represent a single slice or LOD of an image with a byte offset to a tile and X/Y intratile offsets to the given slice. Most of i965 is fine with this but it breaks blorp. This is a terrible way to represent slices of a surface in EGL and we should stop some day but that's a very scary and thorny path. This gets blorp to start working with those surfaces and fixes some dEQP EGL test bugs. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106629 Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/intel/blorp/blorp.c')
-rw-r--r--src/intel/blorp/blorp.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index e348cafb2e5..73f8c67802e 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -137,6 +137,28 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
*/
if (is_render_target && blorp->isl_dev->info->gen <= 6)
info->view.array_len = MIN2(info->view.array_len, 512);
+
+ if (surf->tile_x_sa || surf->tile_y_sa) {
+ /* This is only allowed on simple 2D surfaces without MSAA */
+ assert(info->surf.dim == ISL_SURF_DIM_2D);
+ assert(info->surf.samples == 1);
+ assert(info->surf.levels == 1);
+ assert(info->surf.logical_level0_px.array_len == 1);
+ assert(info->aux_usage == ISL_AUX_USAGE_NONE);
+
+ info->tile_x_sa = surf->tile_x_sa;
+ info->tile_y_sa = surf->tile_y_sa;
+
+ /* Instead of using the X/Y Offset fields in RENDER_SURFACE_STATE, we
+ * place the image at the tile boundary and offset our sampling or
+ * rendering. For this reason, we need to grow the image by the offset
+ * to ensure that the hardware doesn't think we've gone past the edge.
+ */
+ info->surf.logical_level0_px.w += surf->tile_x_sa;
+ info->surf.logical_level0_px.h += surf->tile_y_sa;
+ info->surf.phys_level0_sa.w += surf->tile_x_sa;
+ info->surf.phys_level0_sa.h += surf->tile_y_sa;
+ }
}