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authorPohjolainen, Topi <[email protected]>2017-05-03 12:22:50 +0300
committerJason Ekstrand <[email protected]>2017-05-16 17:04:26 -0700
commit236f17a9f73935db6cddafd91e53a5fae34aae6e (patch)
treeb62cf42de3ddde56f98f282428529f7a5bc83137 /src/intel/Makefile.sources
parentdafc2f1887e192376a176bbd2bb346ad48fc13ae (diff)
intel/isl/gen7: Use stencil vertical alignment of 8 instead of 4
The reasoning Chad gave in the comment for choosing a valign of 4 is entirely bunk. The fact that you have to multiply pitch by 2 is completely unrelated to the halign/valign parameters used for texture layout. (Not completely unrelated. W-tiling is just Y-tiling with a bit of extra swizzling which turns 8x8 W-tiled chunks into 16x4 y-tiled chunks so it makes everything easier if miplevels are always aligned to 8x8.) The fact that RENDER_SURFACE_STATE::SurfaceVerticalAlignmet doesn't have a VALIGN_8 option doesn't matter since this is gen7 and you can't do stencil texturing anyway. v2 (Jason Ekstrand): - Delete most of Chad's comment and add a more descriptive commit message. Signed-off-by: Topi Pohjolainen <[email protected]> Cc: "17.0 17.1" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chad Versace <[email protected]>
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