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authorIan Romanick <[email protected]>2018-02-16 17:26:11 -0800
committerIan Romanick <[email protected]>2018-03-08 15:26:26 -0800
commit360899d4577a2431dc73b5c702d60ac6bd59ca07 (patch)
tree8f018c2161d30ef3857510aae54e72a76e6dd2dc /src/glx/pixel.c
parent52c7df1643ec9af119fd66f916f7fbdbcc798d2d (diff)
i965/vec4: Relax writemask condition in CSE
If the previously seen instruction generates more fields than the new instruction, still allow CSE to happen. This doesn't do much, but it also enables a couple more shaders in the next patch. It helped quite a bit in another change series that I have (at least for now) abandoned. v2: Add some extra comentary about the parameters to instructions_match. Suggested by Ken. No changes on Skylake, Broadwell, Iron Lake or GM45. Ivy Bridge and Haswell had similar results. (Ivy Bridge shown) total instructions in shared programs: 11780295 -> 11780294 (<.01%) instructions in affected programs: 302 -> 301 (-0.33%) helped: 1 HURT: 0 total cycles in shared programs: 257308315 -> 257308313 (<.01%) cycles in affected programs: 2074 -> 2072 (-0.10%) helped: 1 HURT: 0 Sandy Bridge total instructions in shared programs: 10506687 -> 10506686 (<.01%) instructions in affected programs: 335 -> 334 (-0.30%) helped: 1 HURT: 0 Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/glx/pixel.c')
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