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authorRob Clark <[email protected]>2015-06-29 14:49:08 -0400
committerRob Clark <[email protected]>2015-06-30 12:13:44 -0400
commit00b6b41482985ba4a81fbb479a47c06ec83f3797 (patch)
tree550957bcdf4dea96ac052b92971a1320e8608b26 /src/glsl
parent906da495272b1be4c278f5f7402594e3c52521c1 (diff)
freedreno/ir3: cache defining instruction
It is silly to traverse back to find first instruction that writes part of a larger "virtual" register many times per instruction (plus per use as a src to later instructions). Cache this information so we only figure it out once. Signed-off-by: Rob Clark <[email protected]>
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