diff options
| author | Rob Clark <[email protected]> | 2014-05-14 12:46:42 -0400 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2014-05-14 21:26:35 -0400 |
| commit | 670418740fc763f0272b799ea999cd3ff69b1218 (patch) | |
| tree | ba6b872e991b74d6a9360159eb6294f6987728d8 /src/glsl | |
| parent | c37889b5ac77f55b95f5e4b7ad552928c4fe480c (diff) | |
freedreno/a3xx: fix write to bogus register
The loops for updating the multiple packed fields in SP_VS_OUT[] and
SP_VS_VPC_DST[] will zero out one register beyond the last that on
required. Which is normally not a problem (and is kinda convenient
when looking at cmdstream dumps) unless we have maximum (16) varyings.
Fix loop termination condition so that this does not happen.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/glsl')
0 files changed, 0 insertions, 0 deletions