diff options
| author | Kenneth Graunke <[email protected]> | 2015-10-19 11:44:28 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2015-11-13 15:15:41 -0800 |
| commit | 134728fdaef9d2a5d072d25b31437ac0fecd9076 (patch) | |
| tree | e7f64a77d46e769a4872082ddf1a8eba687ed38e /src/glsl/nir/nir_intrinsics.h | |
| parent | c51d7d5fe3425b0b1cb551f47979a1e41f1f73d8 (diff) | |
nir: Allow outputs reads and add the relevant intrinsics.
Normally, we rely on nir_lower_outputs_to_temporaries to create shadow
variables for outputs, buffering the results and writing them all out
at the end of the program. However, this is infeasible for tessellation
control shader outputs.
Tessellation control shaders can generate multiple output vertices, and
write per-vertex outputs. These are arrays indexed by the vertex
number; each thread only writes one element, but can read any other
element - including those being concurrently written by other threads.
The barrier() intrinsic synchronizes between threads.
Even if we tried to shadow every output element (which is of dubious
value), we'd have to read updated values in at barrier() time, which
means we need to allow output reads.
Most stages should continue using nir_lower_outputs_to_temporaries(),
but in theory drivers could choose not to if they really wanted.
v2: Rebase to accomodate Jason's review feedback.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/glsl/nir/nir_intrinsics.h')
| -rw-r--r-- | src/glsl/nir/nir_intrinsics.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/glsl/nir/nir_intrinsics.h b/src/glsl/nir/nir_intrinsics.h index 26ac7ce9cd7..b8d7d6c68cb 100644 --- a/src/glsl/nir/nir_intrinsics.h +++ b/src/glsl/nir/nir_intrinsics.h @@ -255,6 +255,8 @@ LOAD(ubo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) LOAD(input, 0, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) LOAD(per_vertex_input, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER) LOAD(ssbo, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE) +LOAD(output, 0, 1, NIR_INTRINSIC_CAN_ELIMINATE) +LOAD(per_vertex_output, 1, 1, NIR_INTRINSIC_CAN_ELIMINATE) /* * Stores work the same way as loads, except now the first register input is |