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author | Anuj Phogat <[email protected]> | 2015-04-14 22:06:48 -0700 |
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committer | Anuj Phogat <[email protected]> | 2015-06-29 13:15:13 -0700 |
commit | 69ee316c1daf93b4a53b1c02301ffe9df9598d28 (patch) | |
tree | e554d3c359e7f1f16d947aae55d50cdf06b21484 /src/glsl/lower_output_reads.cpp | |
parent | a1afd59662449803fa4a40a79bdf0db16ffcbcf5 (diff) |
i965/gen9: Allocate YF/YS tiled buffer objects
In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
libdrm need not know about the tiling format because these buffers
don't have hardware support to be tiled or detiled through a fenced
region. libdrm still need to know buffer alignment value for its use
in kernel when resolving the relocation.
Using drm_intel_bo_alloc_for_render() for YF/YS tiled buffers
satisfy both the above conditions.
V2: Delete min/max buffer size restrictions not valid for i965+.
Remove redundant align to tile size statements.
Remove some redundant code now when there are no min/max buffer size.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Ben Widawsky <[email protected]>
Diffstat (limited to 'src/glsl/lower_output_reads.cpp')
0 files changed, 0 insertions, 0 deletions