diff options
| author | Marek Olšák <[email protected]> | 2015-01-04 22:16:53 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-01-07 12:06:43 +0100 |
| commit | 02ba7334d35cf8182048c17a149b16f18104c6bf (patch) | |
| tree | 5a402674124cc421d1344b9f680a828eccba6c26 /src/glsl/glsl_parser_extras.h | |
| parent | edf18da85dd3b1865c4faaba650a8fa371b7103c (diff) | |
radeonsi: don't use TC L2 for updating descriptors on SI
It's causing problems, because we mix uncached CP DMA with cached WRITE_DATA
when updating the same memory.
The solution for SI is to use uncached access here, because CP DMA doesn't
support cached access.
CIK will be handled in the next patch.
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/glsl/glsl_parser_extras.h')
0 files changed, 0 insertions, 0 deletions