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authorIago Toral Quiroga <[email protected]>2016-07-19 09:28:04 +0200
committerSamuel Iglesias Gonsálvez <[email protected]>2017-01-03 11:26:51 +0100
commitc3edacaa288ae01c0f37e645737feeeb48f2c3f2 (patch)
treed46e37f5a9e0646937ac519499bb648491de1f3f /src/gbm/main/backend.c
parent2f0bc54e2bf6c7d218f30acc88f5cb94bd6214f7 (diff)
i965/vec4/scalarize_df: do not scalarize swizzles that we can support natively
Certain swizzles like XYZW can be supported by translating only the first two 64-bit swizzle channels to 32-bit channels. This happens with swizzles such that the first two logical components, when translated to 32-bit channels and replicated across the second dvec2 row, select the same channels specified by the 3rd and 4th logical swizzle components. Notice that this opens up the possibility that some instructions are not scalarized and can end up with XY or ZW 32-bit writemasks. Make sure we always scalarize in such cases. Reviewed-by: Matt Turner <[email protected]>
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