diff options
| author | Dave Airlie <[email protected]> | 2015-02-24 14:10:20 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2015-12-02 08:25:00 +1000 |
| commit | af4013d26b3203a794ae34fe0c98139bc1058273 (patch) | |
| tree | 769facfc045d1110bfd951fbb51e7d7019b6a442 /src/gallium | |
| parent | b63944e8b9177d231b3789bf84ea9e67b9629905 (diff) | |
r600: SMX returns CONTEXT_DONE early workaround
streamout, gs rings bug on certain r600s, requires a wait idle
before each surface sync.
Reviewed-by: Marek Olšák <[email protected]>
Cc: "10.6 11.0 11.1" <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/r600/r600_pipe.h | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/r600/r600_state_common.c | 12 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 71a435f8709..c8ee612658e 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -59,7 +59,7 @@ /* the number of CS dwords for flushing and drawing */ #define R600_MAX_FLUSH_CS_DWORDS 16 -#define R600_MAX_DRAW_CS_DWORDS 49 +#define R600_MAX_DRAW_CS_DWORDS 52 #define R600_TRACE_CS_DWORDS 7 #define R600_MAX_USER_CONST_BUFFERS 13 diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 82430e549c7..e50f24ec02a 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -1769,6 +1769,18 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0); } + /* SMX returns CONTEXT_DONE too early workaround */ + if (rctx->b.family == CHIP_R600 || + rctx->b.family == CHIP_RV610 || + rctx->b.family == CHIP_RV630 || + rctx->b.family == CHIP_RV635) { + /* if we have gs shader or streamout + we need to do a wait idle after every draw */ + if (rctx->gs_shader || rctx->b.streamout.streamout_enabled) { + radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); + } + } + /* ES ring rolling over at EOP - workaround */ if (rctx->b.chip_class == R600) { cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); |