diff options
| author | Marek Olšák <[email protected]> | 2015-10-02 19:21:54 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-10-07 19:18:50 +0200 |
| commit | 13e69805ea6a3aa0ec80c2b2430ae4da05c6b1ae (patch) | |
| tree | 4cf9461e708ee86fc0ba37c9a023c6b05a077e5c /src/gallium | |
| parent | 5749676d03d1a4964888a2d9a7624d3b96cc4886 (diff) | |
radeonsi: fix a GS hang on VI
Broken by one of the cleanups: 0d46c3bc9d09b376d74f7399e1a2d1b0a923640b
Not applicable to stable.
Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 3ff4b46251e..2abd5b5a0c3 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -192,6 +192,7 @@ struct si_context { /* Precomputed states. */ struct si_pm4_state *init_config; + bool init_config_has_vgt_flush; struct si_pm4_state *vgt_shader_config[4]; /* With rasterizer discard, there doesn't have to be a pixel shader. * In that case, we bind this one: */ diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 77c585f958e..f673388b121 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1136,6 +1136,20 @@ static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom sctx->force_persample_interp); } +/** + * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that. + */ +static void si_init_config_add_vgt_flush(struct si_context *sctx) +{ + if (sctx->init_config_has_vgt_flush) + return; + + si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE); + si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); + si_pm4_cmd_end(sctx->init_config, false); + sctx->init_config_has_vgt_flush = true; +} + /* Initialize state related to ESGS / GSVS ring buffers */ static void si_init_gs_rings(struct si_context *sctx) { @@ -1156,6 +1170,8 @@ static void si_init_gs_rings(struct si_context *sctx) return; } + si_init_config_add_vgt_flush(sctx); + /* Append these registers to the init config state. */ if (sctx->b.chip_class >= CIK) { if (sctx->b.chip_class >= VI) { @@ -1402,6 +1418,8 @@ static void si_init_tess_factor_ring(struct si_context *sctx) assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0); + si_init_config_add_vgt_flush(sctx); + /* Append these registers to the init config state. */ if (sctx->b.chip_class >= CIK) { si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE, |