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authorIlia Mirkin <imirkin@alum.mit.edu>2014-04-18 02:25:43 -0400
committerIlia Mirkin <imirkin@alum.mit.edu>2014-04-19 13:23:32 -0400
commitba6dcb3c2b8f516b120f591144bf6c3751f0e3f9 (patch)
tree5e7af474b82dd7e53f4c9ed295b3189144e16813 /src/gallium
parent47c19a5819444728b8662da4a0dbd5ca9af4698a (diff)
nouveau/codegen: add missing values for OP_TXLQ into the target arrays
Also rework things so that if someone were to add an opcode without adjusting the values in these arrays, there will be a compilation error. This fixes a few quadop-related piglit regressions since commit d5faf8e78603. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp12
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_target.h4
2 files changed, 9 insertions, 7 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
index 112fca7d152..53c3c3e7cd0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.cpp
@@ -25,7 +25,7 @@
namespace nv50_ir {
-const uint8_t Target::operationSrcNr[OP_LAST + 1] =
+const uint8_t Target::operationSrcNr[] =
{
0, 0, // NOP, PHI
0, 0, 0, 0, // UNION, SPLIT, MERGE, CONSTRAINT
@@ -44,7 +44,7 @@ const uint8_t Target::operationSrcNr[OP_LAST + 1] =
1, 1, 2, 1, 2, // VFETCH, PFETCH, EXPORT, LINTERP, PINTERP
1, 1, // EMIT, RESTART
1, 1, 1, // TEX, TXB, TXL,
- 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TEXCSAA, TEXPREP
+ 1, 1, 1, 1, 1, 1, 2, // TXF, TXQ, TXD, TXG, TXLQ, TEXCSAA, TEXPREP
1, 1, 2, 2, 2, 2, 2, // SULDB, SULDP, SUSTB, SUSTP, SUREDB, SUREDP, SULEA
3, 3, 3, 3, // SUBFM, SUCLAMP, SUEAU, MADSP
0, // TEXBAR
@@ -57,7 +57,7 @@ const uint8_t Target::operationSrcNr[OP_LAST + 1] =
0
};
-const OpClass Target::operationClass[OP_LAST + 1] =
+const OpClass Target::operationClass[] =
{
// NOP; PHI; UNION, SPLIT, MERGE, CONSTRAINT
OPCLASS_OTHER,
@@ -101,10 +101,10 @@ const OpClass Target::operationClass[OP_LAST + 1] =
OPCLASS_SFU, OPCLASS_SFU,
// EMIT, RESTART
OPCLASS_CONTROL, OPCLASS_CONTROL,
- // TEX, TXB, TXL, TXF; TXQ, TXD, TXG, TEXCSAA; TEXPREP
+ // TEX, TXB, TXL, TXF; TXQ, TXD, TXG, TXLQ; TEXCSAA, TEXPREP
OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE,
OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE, OPCLASS_TEXTURE,
- OPCLASS_TEXTURE,
+ OPCLASS_TEXTURE, OPCLASS_TEXTURE,
// SULDB, SULDP, SUSTB, SUSTP; SUREDB, SUREDP, SULEA
OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_ATOMIC, OPCLASS_SURFACE,
OPCLASS_SURFACE, OPCLASS_SURFACE, OPCLASS_SURFACE,
@@ -134,6 +134,8 @@ extern Target *getTargetNV50(unsigned int chipset);
Target *Target::create(unsigned int chipset)
{
+ STATIC_ASSERT(Elements(operationSrcNr) == OP_LAST + 1);
+ STATIC_ASSERT(Elements(operationClass) == OP_LAST + 1);
switch (chipset & ~0xf) {
case 0xc0:
case 0xd0:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
index 9913ca13ddd..9eb0a1fe0fb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
@@ -195,8 +195,8 @@ public:
const bool joinAnterior; // true if join is executed before the op
const bool hasSWSched; // true if code should provide scheduling data
- static const uint8_t operationSrcNr[OP_LAST + 1];
- static const OpClass operationClass[OP_LAST + 1];
+ static const uint8_t operationSrcNr[];
+ static const OpClass operationClass[];
static inline uint8_t getOpSrcNr(operation op)
{