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authorIlia Mirkin <[email protected]>2015-11-21 01:27:01 -0500
committerEmil Velikov <[email protected]>2015-11-29 17:53:31 +0000
commit85b6f905e10a14d15465cd167a04966cc5a0d6cb (patch)
treede7359b7cc7cc9366e37d51dc55444e6733b7fc9 /src/gallium
parent6a6326dcd46545c6885e0b3b3ec5c4e94a9e4dad (diff)
freedreno/a4xx: disable blending and alphatest for integer rt0
Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] (cherry picked from commit 22aeb0c5684cec11fd8cb4a159b10edbcfe8d6ec)
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/freedreno/a4xx/fd4_emit.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
index 8d3112fde3c..017c528cdfd 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_emit.c
@@ -497,11 +497,16 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
}
- if (dirty & FD_DIRTY_ZSA) {
+ if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
+ struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
+ uint32_t rb_alpha_control = zsa->rb_alpha_control;
+
+ if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
+ rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
- OUT_RING(ring, zsa->rb_alpha_control);
+ OUT_RING(ring, rb_alpha_control);
OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
OUT_RING(ring, zsa->rb_stencil_control);
@@ -628,10 +633,16 @@ fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
enum pipe_format format = pipe_surface_format(
ctx->framebuffer.cbufs[i]);
+ bool is_int = util_format_is_pure_integer(format);
bool has_alpha = util_format_has_alpha(format);
uint32_t control = blend->rb_mrt[i].control;
uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
+ if (is_int) {
+ control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
+ control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
+ }
+
if (has_alpha) {
blend_control |= blend->rb_mrt[i].blend_control_rgb;
} else {