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authorMarek Olšák <marek.olsak@amd.com>2018-03-26 17:13:31 -0400
committerMarek Olšák <marek.olsak@amd.com>2018-03-28 18:45:52 -0400
commit3fea237c85c275a0d1e735d3c0a3d9cccefb512e (patch)
tree8cba8f05f3a3e0c617f3c28b20aa79d0f0304e84 /src/gallium
parent3045c5f274206fb4de7549388c0b7a528601a7eb (diff)
radeonsi: don't use the SPI barrier management bug workaround
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_shader.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 8ae742c93f6..00ebbb9b0f2 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7971,6 +7971,11 @@ static bool si_shader_select_ps_parts(struct si_screen *sscreen,
void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
unsigned *lds_size)
{
+ /* If tessellation is all offchip and on-chip GS isn't used, this
+ * workaround is not needed.
+ */
+ return;
+
/* SPI barrier management bug:
* Make sure we have at least 4k of LDS in use to avoid the bug.
* It applies to workgroup sizes of more than one wavefront.