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authorMarek Olšák <[email protected]>2014-01-05 12:48:30 +0100
committerMarek Olšák <[email protected]>2014-01-06 18:40:42 +0100
commit346b6abab9d0ec2d3aec6efe5a4bb03803666c2f (patch)
tree90f92934250010676713d98ac47d6bb1b41240f8 /src/gallium
parentbf3c3611130112062470299c154df2610633683a (diff)
radeonsi: calculate NUM_BANKS for DB correctly on CIK
NUM_BANKS is not constant on CIK. Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c23
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c5
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_winsys.h3
3 files changed, 27 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index b880ee081a6..3666a1106ff 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -40,9 +40,25 @@
#include "../radeon/r600_cs.h"
#include "sid.h"
-static uint32_t cik_num_banks(uint32_t nbanks)
+static uint32_t cik_num_banks(struct r600_screen *rscreen, unsigned bpe, unsigned tile_split)
{
- switch (nbanks) {
+ if (rscreen->b.info.cik_macrotile_mode_array_valid) {
+ unsigned index, tileb;
+
+ tileb = 8 * 8 * bpe;
+ tileb = MIN2(tile_split, tileb);
+
+ for (index = 0; tileb > 64; index++) {
+ tileb >>= 1;
+ }
+
+ assert(index < 16);
+
+ return (rscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
+ }
+
+ /* The old way. */
+ switch (rscreen->b.tiling_info.num_banks) {
case 2:
return V_02803C_ADDR_SURF_2_BANK;
case 4:
@@ -55,7 +71,6 @@ static uint32_t cik_num_banks(uint32_t nbanks)
}
}
-
static unsigned cik_tile_split(unsigned tile_split)
{
switch (tile_split) {
@@ -1800,7 +1815,7 @@ static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
macro_aspect = cik_macro_tile_aspect(macro_aspect);
bankw = cik_bank_wh(bankw);
bankh = cik_bank_wh(bankh);
- nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
+ nbanks = cik_num_banks(rscreen, rtex->surface.bpe, rtex->surface.tile_split);
tile_mode_index = si_tile_mode_index(rtex, level, false);
pipe_config = cik_db_pipe_config(rscreen, tile_mode_index);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 2cd183423b6..dc9d183ae6a 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -423,6 +423,11 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.si_tile_mode_array_valid = TRUE;
}
+ if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
+ ws->info.cik_macrotile_mode_array)) {
+ ws->info.cik_macrotile_mode_array_valid = TRUE;
+ }
+
return TRUE;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 0d0064a6120..55f60d3f412 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -198,6 +198,9 @@ struct radeon_info {
boolean si_tile_mode_array_valid;
uint32_t si_tile_mode_array[32];
+
+ boolean cik_macrotile_mode_array_valid;
+ uint32_t cik_macrotile_mode_array[16];
};
enum radeon_feature_id {