nvc0: bind textures/samplers for compute on Fermi

Textures and samplers don't seem to be aliased between COMPUTE and 3D.

Changes from v2:
 - refactor the code to share (almost) the same logic between 3d and
   compute

Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>

3 files changed, 57 insertions, 8 deletions

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index 83768a2f6f4..70e76ba48b4 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -105,7 +105,17 @@ nvc0_screen_compute_setup(struct nvc0_screen *screen,
    PUSH_DATAh(push, screen->text->offset);
    PUSH_DATA (push, screen->text->offset);
 
-   /* TODO: textures & samplers */
+   /* textures */
+   BEGIN_NVC0(push, NVC0_COMPUTE(TIC_ADDRESS_HIGH), 3);
+   PUSH_DATAh(push, screen->txc->offset);
+   PUSH_DATA (push, screen->txc->offset);
+   PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
+
+   /* samplers */
+   BEGIN_NVC0(push, NVC0_COMPUTE(TSC_ADDRESS_HIGH), 3);
+   PUSH_DATAh(push, screen->txc->offset + 65536);
+   PUSH_DATA (push, screen->txc->offset + 65536);
+   PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 
    return 0;
 }
@@ -139,6 +149,26 @@ nvc0_compute_validate_program(struct nvc0_context *nvc0)
 }
 
 static void
+nvc0_compute_validate_samplers(struct nvc0_context *nvc0)
+{
+   bool need_flush = nvc0_validate_tsc(nvc0, 5);
+   if (need_flush) {
+      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_COMPUTE(TSC_FLUSH), 1);
+      PUSH_DATA (nvc0->base.pushbuf, 0);
+   }
+}
+
+static void
+nvc0_compute_validate_textures(struct nvc0_context *nvc0)
+{
+   bool need_flush = nvc0_validate_tic(nvc0, 5);
+   if (need_flush) {
+      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_COMPUTE(TIC_FLUSH), 1);
+      PUSH_DATA (nvc0->base.pushbuf, 0);
+   }
+}
+
+static void
 nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
 {
    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
@@ -255,8 +285,12 @@ nvc0_compute_state_validate(struct nvc0_context *nvc0)
       nvc0_compute_validate_driverconst(nvc0);
    if (nvc0->dirty_cp & NVC0_NEW_CP_BUFFERS)
       nvc0_compute_validate_buffers(nvc0);
+   if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES)
+      nvc0_compute_validate_textures(nvc0);
+   if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS)
+      nvc0_compute_validate_samplers(nvc0);
 
-   /* TODO: textures, samplers, surfaces, global memory buffers */
+   /* TODO: surfaces, global memory buffers */
 
    nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, false);
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 2b5ab7321d8..7e046c10b32 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -272,6 +272,8 @@ extern void nvc0_clear(struct pipe_context *, unsigned buffers,
 extern void nvc0_init_surface_functions(struct nvc0_context *);
 
 /* nvc0_tex.c */
+bool nvc0_validate_tic(struct nvc0_context *nvc0, int s);
+bool nvc0_validate_tsc(struct nvc0_context *nvc0, int s);
 bool nve4_validate_tsc(struct nvc0_context *nvc0, int s);
 void nvc0_validate_textures(struct nvc0_context *);
 void nvc0_validate_samplers(struct nvc0_context *);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index 6ac60693658..df10a742186 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -23,6 +23,7 @@
 #include "nvc0/nvc0_context.h"
 #include "nvc0/nvc0_resource.h"
 #include "nvc0/gm107_texture.xml.h"
+#include "nvc0/nvc0_compute.xml.h"
 #include "nv50/g80_texture.xml.h"
 #include "nv50/g80_defs.xml.h"
 
@@ -429,7 +430,7 @@ nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
    tic->tic[2] |= address >> 32;
 }
 
-static bool
+bool
 nvc0_validate_tic(struct nvc0_context *nvc0, int s)
 {
    uint32_t commands[32];
@@ -470,7 +471,10 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
          need_flush = true;
       } else
       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
-         BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
+         if (unlikely(s == 5))
+            BEGIN_NVC0(push, NVC0_COMPUTE(TEX_CACHE_CTL), 1);
+         else
+            BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
          PUSH_DATA (push, (tic->id << 4) | 1);
          NOUVEAU_DRV_STAT(&nvc0->screen->base, tex_cache_flush_count, 1);
       }
@@ -483,7 +487,10 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
          continue;
       commands[n++] = (tic->id << 9) | (i << 1) | 1;
 
-      BCTX_REFN(nvc0->bufctx_3d, TEX(s, i), res, RD);
+      if (unlikely(s == 5))
+         BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
+      else
+         BCTX_REFN(nvc0->bufctx_3d, TEX(s, i), res, RD);
    }
    for (; i < nvc0->state.num_textures[s]; ++i)
       commands[n++] = (i << 1) | 0;
@@ -491,7 +498,10 @@ nvc0_validate_tic(struct nvc0_context *nvc0, int s)
    nvc0->state.num_textures[s] = nvc0->num_textures[s];
 
    if (n) {
-      BEGIN_NIC0(push, NVC0_3D(BIND_TIC(s)), n);
+      if (unlikely(s == 5))
+         BEGIN_NIC0(push, NVC0_COMPUTE(BIND_TIC), n);
+      else
+         BEGIN_NIC0(push, NVC0_3D(BIND_TIC(s)), n);
       PUSH_DATAp(push, commands, n);
    }
    nvc0->textures_dirty[s] = 0;
@@ -577,7 +587,7 @@ void nvc0_validate_textures(struct nvc0_context *nvc0)
    }
 }
 
-static bool
+bool
 nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
 {
    uint32_t commands[16];
@@ -614,7 +624,10 @@ nvc0_validate_tsc(struct nvc0_context *nvc0, int s)
    nvc0->state.num_samplers[s] = nvc0->num_samplers[s];
 
    if (n) {
-      BEGIN_NIC0(push, NVC0_3D(BIND_TSC(s)), n);
+      if (unlikely(s == 5))
+         BEGIN_NIC0(push, NVC0_COMPUTE(BIND_TSC), n);
+      else
+         BEGIN_NIC0(push, NVC0_3D(BIND_TSC(s)), n);
       PUSH_DATAp(push, commands, n);
    }
    nvc0->samplers_dirty[s] = 0;