diff options
author | Marek Olšák <[email protected]> | 2017-01-09 16:32:12 +0100 |
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committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
commit | 71eca0780a0cd0794545c1fbfdd96fa4f07c2476 (patch) | |
tree | bf4e5c34e0e78d9b7ce1f899da0d36c6e443e483 /src/gallium | |
parent | b576df401718cf41b64091b97d9c5a7616600093 (diff) |
radeonsi/gfx9: add a scissor bug workaround
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 1ff1547efe7..8c6e9cd1fac 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1169,6 +1169,12 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) if (!si_upload_vertex_buffer_descriptors(sctx)) return; + /* GFX9 scissor bug workaround. There is also a more efficient but + * more involved alternative workaround. */ + if (sctx->b.chip_class == GFX9 && + si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) + sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH; + /* Flush caches before the first state atom, which does L2 prefetches. */ if (sctx->b.flags) si_emit_cache_flush(sctx); |