r600g: finish multi target rendering support

Signed-off-by: Jerome Glisse <[email protected]>

6 files changed, 158 insertions, 38 deletions

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index ae1780a1d40..29dc93bae6c 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -47,14 +47,16 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_screen *rscreen = rctx->screen;
 	static int dc = 0;
+	char dname[256];
 
 	if (radeon_ctx_pm4(rctx->ctx))
 		return;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
-	if (!dc)
-		radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
+	sprintf(dname, "gallium-%08d.bof", dc);
+	if (dc < 10)
+		radeon_ctx_dump_bof(rctx->ctx, dname);
 #if 1
 	radeon_ctx_submit(rctx->ctx);
 #endif
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index dc8d4cb3151..33dff97d22f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -339,7 +339,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 {
 	struct tgsi_full_immediate *immediate;
 	struct r600_shader_ctx ctx;
-	struct r600_bc_output output;
+	struct r600_bc_output output[32];
 	unsigned opcode;
 	int i, r = 0, pos0;
 
@@ -418,33 +418,37 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	}
 	/* export output */
 	for (i = 0, pos0 = 0; i < shader->noutput; i++) {
-		memset(&output, 0, sizeof(struct r600_bc_output));
-		output.gpr = shader->output[i].gpr;
-		output.elem_size = 3;
-		output.swizzle_x = 0;
-		output.swizzle_y = 1;
-		output.swizzle_z = 2;
-		output.swizzle_w = 3;
-		output.barrier = 1;
-		output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
-		output.array_base = i - pos0;
-		output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
+		memset(&output[i], 0, sizeof(struct r600_bc_output));
+		output[i].gpr = shader->output[i].gpr;
+		output[i].elem_size = 3;
+		output[i].swizzle_x = 0;
+		output[i].swizzle_y = 1;
+		output[i].swizzle_z = 2;
+		output[i].swizzle_w = 3;
+		output[i].barrier = 1;
+		output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
+		output[i].array_base = i - pos0;
+		output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
 		switch (ctx.type == TGSI_PROCESSOR_VERTEX) {
 		case TGSI_PROCESSOR_VERTEX:
+			shader->output[i].type = r600_export_parameter;
 			if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-				output.array_base = 60;
-				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
+				shader->output[i].type = r600_export_position;
+				output[i].array_base = 60;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
 				/* position doesn't count in array_base */
 				pos0 = 1;
 			}
 			break;
 		case TGSI_PROCESSOR_FRAGMENT:
+			shader->output[i].type = r600_export_framebuffer;
 			if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
-				output.array_base = 0;
-				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
+				output[i].array_base = 0;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-				output.array_base = 61;
-				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
+				shader->output[i].type = r600_export_position;
+				output[i].array_base = 61;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else {
 				R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
 				r = -EINVAL;
@@ -457,9 +461,17 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			goto out_err;
 		}
 		if (i == (shader->noutput - 1)) {
-			output.end_of_program = 1;
+			output[i].end_of_program = 1;
 		}
-		r = r600_bc_add_output(ctx.bc, &output);
+	}
+	for (i = shader->noutput - 1, shader->output_done = 0; i >= 0; i--) {
+		if (!(shader->output_done & (1 << output[i].type))) {
+			shader->output_done |= (1 << output[i].type);
+			output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
+		}
+	}
+	for (i = 0; i < shader->noutput; i++) {
+		r = r600_bc_add_output(ctx.bc, &output[i]);
 		if (r)
 			goto out_err;
 	}
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index ee0381e8bdd..15562c19a52 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -25,9 +25,17 @@
 
 #include "r600_asm.h"
 
+enum r600_export_type {
+	r600_export_position = 0,
+	r600_export_parameter,
+	r600_export_framebuffer,
+};
+
 struct r600_shader_io {
 	unsigned		name;
 	unsigned		gpr;
+	unsigned		done;
+	unsigned		type;
 	int			sid;
 	unsigned		interpolate;
 };
@@ -41,6 +49,7 @@ struct r600_shader {
 	struct r600_shader_io	input[32];
 	struct r600_shader_io	output[32];
 	enum radeon_family	family;
+	unsigned		output_done;
 };
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index deb9bf3395a..ef6c1bedeb4 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -675,9 +675,8 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	unsigned color_info;
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
-	int id = R600_CB0 + cb;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, id);
+	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
 	if (rstate == NULL)
 		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 3a8405f9b40..00cff41b4fd 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -160,8 +160,8 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
  * R600/R700
  */
 
-#define R600_NSTATE				1273
-#define R600_NTYPE				25
+#define R600_NSTATE				1280
+#define R600_NTYPE				32
 
 #define R600_CONFIG				0
 #define R600_CONFIG_TYPE				0
@@ -207,12 +207,26 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
 #define R600_GS_SAMPLER_BORDER_TYPE				20
 #define R600_CB0				1269
 #define R600_CB0_TYPE				21
-#define R600_DB				1270
-#define R600_DB_TYPE				22
-#define R600_VGT				1271
-#define R600_VGT_TYPE				23
-#define R600_DRAW				1272
-#define R600_DRAW_TYPE				24
+#define R600_CB1				1270
+#define R600_CB1_TYPE				22
+#define R600_CB2				1271
+#define R600_CB2_TYPE				23
+#define R600_CB3				1272
+#define R600_CB3_TYPE				24
+#define R600_CB4				1273
+#define R600_CB4_TYPE				25
+#define R600_CB5				1274
+#define R600_CB5_TYPE				26
+#define R600_CB6				1275
+#define R600_CB6_TYPE				27
+#define R600_CB7				1276
+#define R600_CB7_TYPE				28
+#define R600_DB				1277
+#define R600_DB_TYPE				29
+#define R600_VGT				1278
+#define R600_VGT_TYPE				30
+#define R600_DRAW				1279
+#define R600_DRAW_TYPE				31
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			1
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 5896df21b21..e40c77d8f6c 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -372,6 +372,76 @@ static const struct radeon_register R600_CB0_names[] = {
 	{0x00028100, 0, 0, "CB_COLOR0_MASK"},
 };
 
+static const struct radeon_register R600_CB1_names[] = {
+	{0x00028044, 1, 0, "CB_COLOR1_BASE"},
+	{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
+	{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
+	{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
+	{0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
+	{0x000280C4, 1, 2, "CB_COLOR1_TILE"},
+	{0x00028104, 0, 0, "CB_COLOR1_MASK"},
+};
+
+static const struct radeon_register R600_CB2_names[] = {
+	{0x00028048, 1, 0, "CB_COLOR2_BASE"},
+	{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
+	{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
+	{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
+	{0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
+	{0x000280C8, 1, 2, "CB_COLOR2_TILE"},
+	{0x00028108, 0, 0, "CB_COLOR2_MASK"},
+};
+
+static const struct radeon_register R600_CB3_names[] = {
+	{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
+	{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
+	{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
+	{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
+	{0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
+	{0x000280CC, 1, 2, "CB_COLOR3_TILE"},
+	{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
+};
+
+static const struct radeon_register R600_CB4_names[] = {
+	{0x00028050, 1, 0, "CB_COLOR4_BASE"},
+	{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
+	{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
+	{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
+	{0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
+	{0x000280D0, 1, 2, "CB_COLOR4_TILE"},
+	{0x00028110, 0, 0, "CB_COLOR4_MASK"},
+};
+
+static const struct radeon_register R600_CB5_names[] = {
+	{0x00028054, 1, 0, "CB_COLOR5_BASE"},
+	{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
+	{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
+	{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
+	{0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
+	{0x000280D4, 1, 2, "CB_COLOR5_TILE"},
+	{0x00028114, 0, 0, "CB_COLOR5_MASK"},
+};
+
+static const struct radeon_register R600_CB6_names[] = {
+	{0x00028058, 1, 0, "CB_COLOR6_BASE"},
+	{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
+	{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
+	{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
+	{0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
+	{0x000280D8, 1, 2, "CB_COLOR6_TILE"},
+	{0x00028118, 0, 0, "CB_COLOR6_MASK"},
+};
+
+static const struct radeon_register R600_CB7_names[] = {
+	{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
+	{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
+	{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
+	{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
+	{0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
+	{0x000280DC, 1, 2, "CB_COLOR7_TILE"},
+	{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
+};
+
 static const struct radeon_register R600_DB_names[] = {
 	{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
 	{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
@@ -425,9 +495,16 @@ static struct radeon_type R600_types[] = {
 	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
 	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
 	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 static struct radeon_type R700_types[] = {
@@ -453,9 +530,16 @@ static struct radeon_type R700_types[] = {
 	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
 	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
 	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 #endif