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authorKenneth Graunke <[email protected]>2019-02-15 11:00:39 -0800
committerKenneth Graunke <[email protected]>2019-02-19 15:56:19 -0800
commitba7519ca36ce0de74657b01fe4fa2c97aace538e (patch)
treee3cc10318f323a2c90641f66d4300f1876524c40 /src/gallium
parent9c4d5926aa9cf0f8f5e0e163845b20b83f02b515 (diff)
radeonsi: Go back to using llvm.pow intrinsic for nir_op_fpow
ARB_vertex_program and ARB_fragment_program define 0^0 = 1 (while GLSL leaves it undefined). Performing fpow lowering in NIR would break this behavior, preventing us from using prog_to_nir. According to llvm/lib/Target/AMDGPU/SIInstructions.td, POW_common expands to <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>, which presumably does a zero-wins multiply. Lowering in NIR results in a non-legacy multiply, where: pow(0, 0) = 2^(log2(0) * 0) = 2^(-INF * 0) = 2^(-NaN) = -NaN which isn't the desired result. This reverts: - commit d6b75392067712908bdc372f1007e085439bf9f5 (ac/nir: remove emission of nir_op_fpow) - commit 22430224fec31591432d4a3e65c6f457ba1c1653 (radeonsi/nir: enable lowering of fpow) and prevents a regression in gl-1.0-spot-light with AMD_DEBUG=nir after enabling prog_to_nir in st/mesa later in this series. Reviewed-by: Timothy Arceri <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_get.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index f8ca02d4fcf..a5cb209b59e 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -486,7 +486,6 @@ static const struct nir_shader_compiler_options nir_options = {
.lower_scmp = true,
.lower_flrp32 = true,
.lower_flrp64 = true,
- .lower_fpow = true,
.lower_fsat = true,
.lower_fdiv = true,
.lower_sub = true,