diff options
| author | Marek Olšák <[email protected]> | 2016-04-16 14:41:57 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-04-22 01:30:39 +0200 |
| commit | af249a7da9bf2621ab836d5074ef692677b11bbf (patch) | |
| tree | 5e006ea5552461b793fe85b9c3c91f86fa716c45 /src/gallium | |
| parent | fb523cb6ad3ffef22ab4b9cce9e53859c17c5739 (diff) | |
gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*
Acked-by: Jose Fonseca <[email protected]>
Diffstat (limited to 'src/gallium')
43 files changed, 305 insertions, 314 deletions
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c index e3943c7d528..31157a83409 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c @@ -2113,7 +2113,7 @@ lp_build_lod_property( reg->Register.File == TGSI_FILE_IMMEDIATE) { lod_property = LP_SAMPLER_LOD_SCALAR; } - else if (bld_base->info->processor == TGSI_PROCESSOR_FRAGMENT) { + else if (bld_base->info->processor == PIPE_SHADER_FRAGMENT) { if (gallivm_debug & GALLIVM_DEBUG_NO_QUAD_LOD) { lod_property = LP_SAMPLER_LOD_PER_ELEMENT; } @@ -2301,7 +2301,7 @@ emit_tex( struct lp_build_tgsi_soa_context *bld, * could also check all src regs if constant but I doubt such * cases exist in practice. */ - if (bld->bld_base.info->processor == TGSI_PROCESSOR_FRAGMENT) { + if (bld->bld_base.info->processor == PIPE_SHADER_FRAGMENT) { if (gallivm_debug & GALLIVM_DEBUG_NO_QUAD_LOD) { lod_property = LP_SAMPLER_LOD_PER_ELEMENT; } @@ -2469,7 +2469,7 @@ emit_sample(struct lp_build_tgsi_soa_context *bld, * could also check all src regs if constant but I doubt such * cases exist in practice. */ - if (bld->bld_base.info->processor == TGSI_PROCESSOR_FRAGMENT) { + if (bld->bld_base.info->processor == PIPE_SHADER_FRAGMENT) { if (gallivm_debug & GALLIVM_DEBUG_NO_QUAD_LOD) { lod_property = LP_SAMPLER_LOD_PER_ELEMENT; } diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c index d76b6d900ce..e2b305ecb37 100644 --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c @@ -338,7 +338,7 @@ ttn_emit_declaration(struct ttn_compile *c) var->data.mode = nir_var_shader_in; var->name = ralloc_asprintf(var, "in_%d", idx); - if (c->scan->processor == TGSI_PROCESSOR_FRAGMENT) { + if (c->scan->processor == PIPE_SHADER_FRAGMENT) { var->data.location = tgsi_varying_semantic_to_slot(decl->Semantic.Name, decl->Semantic.Index); @@ -381,7 +381,7 @@ ttn_emit_declaration(struct ttn_compile *c) var->name = ralloc_asprintf(var, "out_%d", idx); var->data.index = 0; - if (c->scan->processor == TGSI_PROCESSOR_FRAGMENT) { + if (c->scan->processor == PIPE_SHADER_FRAGMENT) { switch (semantic_name) { case TGSI_SEMANTIC_COLOR: { /* TODO tgsi loses some information, so we cannot @@ -1920,12 +1920,12 @@ static gl_shader_stage tgsi_processor_to_shader_stage(unsigned processor) { switch (processor) { - case TGSI_PROCESSOR_FRAGMENT: return MESA_SHADER_FRAGMENT; - case TGSI_PROCESSOR_VERTEX: return MESA_SHADER_VERTEX; - case TGSI_PROCESSOR_GEOMETRY: return MESA_SHADER_GEOMETRY; - case TGSI_PROCESSOR_TESS_CTRL: return MESA_SHADER_TESS_CTRL; - case TGSI_PROCESSOR_TESS_EVAL: return MESA_SHADER_TESS_EVAL; - case TGSI_PROCESSOR_COMPUTE: return MESA_SHADER_COMPUTE; + case PIPE_SHADER_FRAGMENT: return MESA_SHADER_FRAGMENT; + case PIPE_SHADER_VERTEX: return MESA_SHADER_VERTEX; + case PIPE_SHADER_GEOMETRY: return MESA_SHADER_GEOMETRY; + case PIPE_SHADER_TESS_CTRL: return MESA_SHADER_TESS_CTRL; + case PIPE_SHADER_TESS_EVAL: return MESA_SHADER_TESS_EVAL; + case PIPE_SHADER_COMPUTE: return MESA_SHADER_COMPUTE; default: unreachable("invalid TGSI processor"); } diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.c b/src/gallium/auxiliary/tgsi/tgsi_dump.c index 6d39ef21083..f57f2bbcc18 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_dump.c +++ b/src/gallium/auxiliary/tgsi/tgsi_dump.c @@ -295,17 +295,17 @@ iter_declaration( * two dimensional */ if (decl->Declaration.File == TGSI_FILE_INPUT && - (iter->processor.Processor == TGSI_PROCESSOR_GEOMETRY || + (iter->processor.Processor == PIPE_SHADER_GEOMETRY || (!patch && - (iter->processor.Processor == TGSI_PROCESSOR_TESS_CTRL || - iter->processor.Processor == TGSI_PROCESSOR_TESS_EVAL)))) { + (iter->processor.Processor == PIPE_SHADER_TESS_CTRL || + iter->processor.Processor == PIPE_SHADER_TESS_EVAL)))) { TXT("[]"); } /* all non-patch tess ctrl shader outputs are two dimensional */ if (decl->Declaration.File == TGSI_FILE_OUTPUT && !patch && - iter->processor.Processor == TGSI_PROCESSOR_TESS_CTRL) { + iter->processor.Processor == PIPE_SHADER_TESS_CTRL) { TXT("[]"); } @@ -394,7 +394,7 @@ iter_declaration( } if (decl->Declaration.Interpolate) { - if (iter->processor.Processor == TGSI_PROCESSOR_FRAGMENT && + if (iter->processor.Processor == PIPE_SHADER_FRAGMENT && decl->Declaration.File == TGSI_FILE_INPUT) { TXT( ", " ); diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c index 41dd0f0466a..002aefca566 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.c +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c @@ -899,7 +899,7 @@ tgsi_exec_machine_bind_shader( mach->ImmLimit = 0; mach->NumOutputs = 0; - if (mach->Processor == TGSI_PROCESSOR_GEOMETRY && + if (mach->Processor == PIPE_SHADER_GEOMETRY && !mach->UsedGeometryShader) { struct tgsi_exec_vector *inputs; struct tgsi_exec_vector *outputs; @@ -1005,7 +1005,7 @@ tgsi_exec_machine_bind_shader( break; case TGSI_TOKEN_TYPE_PROPERTY: - if (mach->Processor == TGSI_PROCESSOR_GEOMETRY) { + if (mach->Processor == PIPE_SHADER_GEOMETRY) { if (parse.FullToken.FullProperty.Property.PropertyName == TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES) { mach->MaxOutputVertices = parse.FullToken.FullProperty.u[0].Data; } @@ -1260,7 +1260,7 @@ fetch_src_file_channel(const struct tgsi_exec_machine *mach, case TGSI_FILE_INPUT: for (i = 0; i < TGSI_QUAD_SIZE; i++) { /* - if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) { + if (PIPE_SHADER_GEOMETRY == mach->Processor) { debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n", index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i], index2D->i[i], index->i[i]); @@ -1654,7 +1654,7 @@ store_dest_dstret(struct tgsi_exec_machine *mach, debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n", mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0], reg->Register.Index); - if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) { + if (PIPE_SHADER_GEOMETRY == mach->Processor) { debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask); for (i = 0; i < TGSI_QUAD_SIZE; i++) if (execmask & (1 << i)) @@ -1888,7 +1888,7 @@ emit_primitive(struct tgsi_exec_machine *mach) static void conditional_emit_primitive(struct tgsi_exec_machine *mach) { - if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) { + if (PIPE_SHADER_GEOMETRY == mach->Processor) { int emitted_verts = mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]; if (emitted_verts) { @@ -2699,7 +2699,7 @@ exec_declaration(struct tgsi_exec_machine *mach, return; } - if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) { + if (mach->Processor == PIPE_SHADER_FRAGMENT) { if (decl->Declaration.File == TGSI_FILE_INPUT) { uint first, last, mask; @@ -5663,7 +5663,7 @@ tgsi_exec_machine_run( struct tgsi_exec_machine *mach ) mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0; mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0; - if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) { + if( mach->Processor == PIPE_SHADER_GEOMETRY ) { mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0; mach->Primitives[0] = 0; /* GS runs on a single primitive for now */ @@ -5760,7 +5760,7 @@ tgsi_exec_machine_run( struct tgsi_exec_machine *mach ) #if 0 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */ - if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) { + if (mach->Processor == PIPE_SHADER_FRAGMENT) { /* * Scale back depth component. */ diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 42fb922baa5..d02a45a3ef8 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -371,7 +371,7 @@ struct tgsi_exec_machine unsigned ConstsSize[PIPE_MAX_CONSTANT_BUFFERS]; const struct tgsi_token *Tokens; /**< Declarations, instructions */ - unsigned Processor; /**< TGSI_PROCESSOR_x */ + unsigned Processor; /**< PIPE_SHADER_x */ /* GEOMETRY processor only. */ unsigned *Primitives; diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c index 462bd15f01c..292d70ff8b0 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info.c +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c @@ -296,15 +296,15 @@ const char * tgsi_get_processor_name( uint processor ) { switch (processor) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: return "vertex shader"; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: return "fragment shader"; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: return "geometry shader"; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: return "tessellation control shader"; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: return "tessellation evaluation shader"; default: return "unknown shader type!"; diff --git a/src/gallium/auxiliary/tgsi/tgsi_lowering.c b/src/gallium/auxiliary/tgsi/tgsi_lowering.c index d54f4b91bb1..b0a28f27107 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_lowering.c +++ b/src/gallium/auxiliary/tgsi/tgsi_lowering.c @@ -1615,7 +1615,7 @@ tgsi_transform_lowering(const struct tgsi_lowering_config *config, * color, then figure out the number of additional inputs we need * to create for BCOLOR's.. */ - if ((info->processor == TGSI_PROCESSOR_FRAGMENT) && + if ((info->processor == PIPE_SHADER_FRAGMENT) && config->color_two_side) { int i; ctx.face_idx = -1; diff --git a/src/gallium/auxiliary/tgsi/tgsi_sanity.c b/src/gallium/auxiliary/tgsi/tgsi_sanity.c index 88ecb2a31cb..f867925ef58 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_sanity.c +++ b/src/gallium/auxiliary/tgsi/tgsi_sanity.c @@ -414,9 +414,9 @@ iter_declaration( decl->Semantic.Name == TGSI_SEMANTIC_TESSOUTER || decl->Semantic.Name == TGSI_SEMANTIC_TESSINNER; if (file == TGSI_FILE_INPUT && !patch && ( - processor == TGSI_PROCESSOR_GEOMETRY || - processor == TGSI_PROCESSOR_TESS_CTRL || - processor == TGSI_PROCESSOR_TESS_EVAL)) { + processor == PIPE_SHADER_GEOMETRY || + processor == PIPE_SHADER_TESS_CTRL || + processor == PIPE_SHADER_TESS_EVAL)) { uint vert; for (vert = 0; vert < ctx->implied_array_size; ++vert) { scan_register *reg = MALLOC(sizeof(scan_register)); @@ -424,7 +424,7 @@ iter_declaration( check_and_declare(ctx, reg); } } else if (file == TGSI_FILE_OUTPUT && !patch && - processor == TGSI_PROCESSOR_TESS_CTRL) { + processor == PIPE_SHADER_TESS_CTRL) { uint vert; for (vert = 0; vert < ctx->implied_out_array_size; ++vert) { scan_register *reg = MALLOC(sizeof(scan_register)); @@ -485,11 +485,11 @@ iter_property( { struct sanity_check_ctx *ctx = (struct sanity_check_ctx *) iter; - if (iter->processor.Processor == TGSI_PROCESSOR_GEOMETRY && + if (iter->processor.Processor == PIPE_SHADER_GEOMETRY && prop->Property.PropertyName == TGSI_PROPERTY_GS_INPUT_PRIM) { ctx->implied_array_size = u_vertices_per_prim(prop->u[0].Data); } - if (iter->processor.Processor == TGSI_PROCESSOR_TESS_CTRL && + if (iter->processor.Processor == PIPE_SHADER_TESS_CTRL && prop->Property.PropertyName == TGSI_PROPERTY_TCS_VERTICES_OUT) ctx->implied_out_array_size = prop->u[0].Data; return TRUE; @@ -499,8 +499,8 @@ static boolean prolog(struct tgsi_iterate_context *iter) { struct sanity_check_ctx *ctx = (struct sanity_check_ctx *) iter; - if (iter->processor.Processor == TGSI_PROCESSOR_TESS_CTRL || - iter->processor.Processor == TGSI_PROCESSOR_TESS_EVAL) + if (iter->processor.Processor == PIPE_SHADER_TESS_CTRL || + iter->processor.Processor == PIPE_SHADER_TESS_EVAL) ctx->implied_array_size = 32; return TRUE; } diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c b/src/gallium/auxiliary/tgsi/tgsi_scan.c index c5ef16810a2..ab8126230f0 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_scan.c +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c @@ -163,7 +163,7 @@ scan_instruction(struct tgsi_shader_info *info, info->input_usage_mask[ind] |= usage_mask; } - if (info->processor == TGSI_PROCESSOR_FRAGMENT && + if (info->processor == PIPE_SHADER_FRAGMENT && !src->Register.Indirect) { unsigned name = info->input_semantic_name[src->Register.Index]; @@ -320,7 +320,7 @@ scan_declaration(struct tgsi_shader_info *info, info->input_cylindrical_wrap[reg] = (ubyte)fulldecl->Interp.CylindricalWrap; /* Vertex shaders can have inputs with holes between them. */ - if (info->processor == TGSI_PROCESSOR_VERTEX) + if (info->processor == PIPE_SHADER_VERTEX) info->num_inputs = MAX2(info->num_inputs, reg + 1); else { info->num_inputs++; @@ -372,7 +372,7 @@ scan_declaration(struct tgsi_shader_info *info, if (semName == TGSI_SEMANTIC_PRIMID) info->uses_primid = TRUE; - else if (procType == TGSI_PROCESSOR_FRAGMENT) { + else if (procType == PIPE_SHADER_FRAGMENT) { if (semName == TGSI_SEMANTIC_POSITION) info->reads_position = TRUE; else if (semName == TGSI_SEMANTIC_FACE) @@ -424,10 +424,10 @@ scan_declaration(struct tgsi_shader_info *info, if (semName == TGSI_SEMANTIC_COLOR) info->colors_written |= 1 << semIndex; - if (procType == TGSI_PROCESSOR_VERTEX || - procType == TGSI_PROCESSOR_GEOMETRY || - procType == TGSI_PROCESSOR_TESS_CTRL || - procType == TGSI_PROCESSOR_TESS_EVAL) { + if (procType == PIPE_SHADER_VERTEX || + procType == PIPE_SHADER_GEOMETRY || + procType == PIPE_SHADER_TESS_CTRL || + procType == PIPE_SHADER_TESS_EVAL) { switch (semName) { case TGSI_SEMANTIC_VIEWPORT_INDEX: info->writes_viewport_index = TRUE; @@ -444,7 +444,7 @@ scan_declaration(struct tgsi_shader_info *info, } } - if (procType == TGSI_PROCESSOR_FRAGMENT) { + if (procType == PIPE_SHADER_FRAGMENT) { switch (semName) { case TGSI_SEMANTIC_POSITION: info->writes_z = TRUE; @@ -458,7 +458,7 @@ scan_declaration(struct tgsi_shader_info *info, } } - if (procType == TGSI_PROCESSOR_VERTEX) { + if (procType == PIPE_SHADER_VERTEX) { if (semName == TGSI_SEMANTIC_EDGEFLAG) { info->writes_edgeflag = TRUE; } @@ -549,12 +549,12 @@ tgsi_scan_shader(const struct tgsi_token *tokens, return; } procType = parse.FullHeader.Processor.Processor; - assert(procType == TGSI_PROCESSOR_FRAGMENT || - procType == TGSI_PROCESSOR_VERTEX || - procType == TGSI_PROCESSOR_GEOMETRY || - procType == TGSI_PROCESSOR_TESS_CTRL || - procType == TGSI_PROCESSOR_TESS_EVAL || - procType == TGSI_PROCESSOR_COMPUTE); + assert(procType == PIPE_SHADER_FRAGMENT || + procType == PIPE_SHADER_VERTEX || + procType == PIPE_SHADER_GEOMETRY || + procType == PIPE_SHADER_TESS_CTRL || + procType == PIPE_SHADER_TESS_EVAL || + procType == PIPE_SHADER_COMPUTE); info->processor = procType; /** @@ -590,7 +590,7 @@ tgsi_scan_shader(const struct tgsi_token *tokens, /* The dimensions of the IN decleration in geometry shader have * to be deduced from the type of the input primitive. */ - if (procType == TGSI_PROCESSOR_GEOMETRY) { + if (procType == PIPE_SHADER_GEOMETRY) { unsigned input_primitive = info->properties[TGSI_PROPERTY_GS_INPUT_PRIM]; int num_verts = u_vertices_per_prim(input_primitive); diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c b/src/gallium/auxiliary/tgsi/tgsi_strings.c index d613f5e8cfb..894d47501de 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_strings.c +++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c @@ -34,8 +34,8 @@ const char *tgsi_processor_type_names[6] = { - "FRAG", "VERT", + "FRAG", "GEOM", "TESS_CTRL", "TESS_EVAL", diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c b/src/gallium/auxiliary/tgsi/tgsi_text.c index 028633c9412..114e6e5aab4 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_text.c +++ b/src/gallium/auxiliary/tgsi/tgsi_text.c @@ -301,17 +301,17 @@ static boolean parse_header( struct translate_ctx *ctx ) uint processor; if (str_match_nocase_whole( &ctx->cur, "FRAG" )) - processor = TGSI_PROCESSOR_FRAGMENT; + processor = PIPE_SHADER_FRAGMENT; else if (str_match_nocase_whole( &ctx->cur, "VERT" )) - processor = TGSI_PROCESSOR_VERTEX; + processor = PIPE_SHADER_VERTEX; else if (str_match_nocase_whole( &ctx->cur, "GEOM" )) - processor = TGSI_PROCESSOR_GEOMETRY; + processor = PIPE_SHADER_GEOMETRY; else if (str_match_nocase_whole( &ctx->cur, "TESS_CTRL" )) - processor = TGSI_PROCESSOR_TESS_CTRL; + processor = PIPE_SHADER_TESS_CTRL; else if (str_match_nocase_whole( &ctx->cur, "TESS_EVAL" )) - processor = TGSI_PROCESSOR_TESS_EVAL; + processor = PIPE_SHADER_TESS_EVAL; else if (str_match_nocase_whole( &ctx->cur, "COMP" )) - processor = TGSI_PROCESSOR_COMPUTE; + processor = PIPE_SHADER_COMPUTE; else { report_error( ctx, "Unknown header" ); return FALSE; @@ -698,9 +698,9 @@ parse_register_dcl( * the second bracket */ /* tessellation has similar constraints to geometry shader */ - if ((ctx->processor == TGSI_PROCESSOR_GEOMETRY && is_in) || - (ctx->processor == TGSI_PROCESSOR_TESS_EVAL && is_in) || - (ctx->processor == TGSI_PROCESSOR_TESS_CTRL && (is_in || is_out))) { + if ((ctx->processor == PIPE_SHADER_GEOMETRY && is_in) || + (ctx->processor == PIPE_SHADER_TESS_EVAL && is_in) || + (ctx->processor == PIPE_SHADER_TESS_CTRL && (is_in || is_out))) { brackets[0] = brackets[1]; *num_brackets = 1; } else { @@ -1241,7 +1241,7 @@ static boolean parse_declaration( struct translate_ctx *ctx ) } is_vs_input = (file == TGSI_FILE_INPUT && - ctx->processor == TGSI_PROCESSOR_VERTEX); + ctx->processor == PIPE_SHADER_VERTEX); cur = ctx->cur; eat_opt_white( &cur ); @@ -1655,7 +1655,7 @@ static boolean parse_property( struct translate_ctx *ctx ) return FALSE; } if (property_name == TGSI_PROPERTY_GS_INPUT_PRIM && - ctx->processor == TGSI_PROCESSOR_GEOMETRY) { + ctx->processor == PIPE_SHADER_GEOMETRY) { ctx->implied_array_size = u_vertices_per_prim(values[0]); } break; @@ -1703,8 +1703,8 @@ static boolean translate( struct translate_ctx *ctx ) if (!parse_header( ctx )) return FALSE; - if (ctx->processor == TGSI_PROCESSOR_TESS_CTRL || - ctx->processor == TGSI_PROCESSOR_TESS_EVAL) + if (ctx->processor == PIPE_SHADER_TESS_CTRL || + ctx->processor == PIPE_SHADER_TESS_EVAL) ctx->implied_array_size = 32; while (*ctx->cur != '\0') { diff --git a/src/gallium/auxiliary/tgsi/tgsi_transform.c b/src/gallium/auxiliary/tgsi/tgsi_transform.c index 9d316ccb9e3..ffdad1338c5 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_transform.c +++ b/src/gallium/auxiliary/tgsi/tgsi_transform.c @@ -137,9 +137,9 @@ tgsi_transform_shader(const struct tgsi_token *tokens_in, return -1; } procType = parse.FullHeader.Processor.Processor; - assert(procType == TGSI_PROCESSOR_FRAGMENT || - procType == TGSI_PROCESSOR_VERTEX || - procType == TGSI_PROCESSOR_GEOMETRY); + assert(procType == PIPE_SHADER_FRAGMENT || + procType == PIPE_SHADER_VERTEX || + procType == PIPE_SHADER_GEOMETRY); /** diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c b/src/gallium/auxiliary/tgsi/tgsi_ureg.c index 297e257b322..17b39e20ed8 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c +++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c @@ -317,7 +317,7 @@ struct ureg_src ureg_DECL_vs_input( struct ureg_program *ureg, unsigned index ) { - assert(ureg->processor == TGSI_PROCESSOR_VERTEX); + assert(ureg->processor == PIPE_SHADER_VERTEX); assert(index / 32 < ARRAY_SIZE(ureg->vs_inputs)); ureg->vs_inputs[index/32] |= 1 << (index % 32); @@ -1733,13 +1733,13 @@ static void emit_decls( struct ureg_program *ureg ) if (ureg->properties[i] != ~0) emit_property(ureg, i, ureg->properties[i]); - if (ureg->processor == TGSI_PROCESSOR_VERTEX) { + if (ureg->processor == PIPE_SHADER_VERTEX) { for (i = 0; i < PIPE_MAX_ATTRIBS; i++) { if (ureg->vs_inputs[i/32] & (1 << (i%32))) { emit_decl_range( ureg, TGSI_FILE_INPUT, i, 1 ); } } - } else if (ureg->processor == TGSI_PROCESSOR_FRAGMENT) { + } else if (ureg->processor == PIPE_SHADER_FRAGMENT) { if (ureg->supports_any_inout_decl_range) { for (i = 0; i < ureg->nr_inputs; i++) { emit_decl_fs(ureg, @@ -1971,11 +1971,11 @@ const struct tgsi_token *ureg_finalize( struct ureg_program *ureg ) const struct tgsi_token *tokens; switch (ureg->processor) { - case TGSI_PROCESSOR_VERTEX: - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_TESS_EVAL: ureg_property(ureg, TGSI_PROPERTY_NEXT_SHADER, ureg->next_shader_processor == -1 ? - TGSI_PROCESSOR_FRAGMENT : + PIPE_SHADER_FRAGMENT : ureg->next_shader_processor); break; } @@ -2029,15 +2029,15 @@ void *ureg_create_shader( struct ureg_program *ureg, memset(&state.stream_output, 0, sizeof(state.stream_output)); switch (ureg->processor) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: return pipe->create_vs_state(pipe, &state); - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: return pipe->create_tcs_state(pipe, &state); - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: return pipe->create_tes_state(pipe, &state); - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: return pipe->create_gs_state(pipe, &state); - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: return pipe->create_fs_state(pipe, &state); default: return NULL; diff --git a/src/gallium/auxiliary/util/u_inlines.h b/src/gallium/auxiliary/util/u_inlines.h index 0e80cef0b08..eedd32e9e47 100644 --- a/src/gallium/auxiliary/util/u_inlines.h +++ b/src/gallium/auxiliary/util/u_inlines.h @@ -654,17 +654,17 @@ static inline unsigned util_pipe_shader_from_tgsi_processor(unsigned processor) { switch (processor) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: return PIPE_SHADER_VERTEX; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: return PIPE_SHADER_TESS_CTRL; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: return PIPE_SHADER_TESS_EVAL; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: return PIPE_SHADER_GEOMETRY; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: return PIPE_SHADER_FRAGMENT; - case TGSI_PROCESSOR_COMPUTE: + case PIPE_SHADER_COMPUTE: return PIPE_SHADER_COMPUTE; default: assert(0); diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c b/src/gallium/auxiliary/util/u_simple_shaders.c index 76950a1a9cf..8c739da1ee8 100644 --- a/src/gallium/auxiliary/util/u_simple_shaders.c +++ b/src/gallium/auxiliary/util/u_simple_shaders.c @@ -79,7 +79,7 @@ util_make_vertex_passthrough_shader_with_so(struct pipe_context *pipe, struct ureg_program *ureg; uint i; - ureg = ureg_create( TGSI_PROCESSOR_VERTEX ); + ureg = ureg_create( PIPE_SHADER_VERTEX ); if (!ureg) return NULL; @@ -227,7 +227,7 @@ util_make_fragment_tex_shader_writemask(struct pipe_context *pipe, assert(interp_mode == TGSI_INTERPOLATE_LINEAR || interp_mode == TGSI_INTERPOLATE_PERSPECTIVE); - ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT ); + ureg = ureg_create( PIPE_SHADER_FRAGMENT ); if (!ureg) return NULL; @@ -297,7 +297,7 @@ util_make_fragment_tex_shader_writedepth(struct pipe_context *pipe, struct ureg_dst out, depth; struct ureg_src imm; - ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT ); + ureg = ureg_create( PIPE_SHADER_FRAGMENT ); if (!ureg) return NULL; @@ -349,7 +349,7 @@ util_make_fragment_tex_shader_writedepthstencil(struct pipe_context *pipe, struct ureg_dst out, depth, stencil; struct ureg_src imm; - ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT ); + ureg = ureg_create( PIPE_SHADER_FRAGMENT ); if (!ureg) return NULL; @@ -413,7 +413,7 @@ util_make_fragment_tex_shader_writestencil(struct pipe_context *pipe, struct ureg_dst out, stencil; struct ureg_src imm; - ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT ); + ureg = ureg_create( PIPE_SHADER_FRAGMENT ); if (!ureg) return NULL; @@ -493,7 +493,7 @@ util_make_fragment_passthrough_shader(struct pipe_context *pipe, void * util_make_empty_fragment_shader(struct pipe_context *pipe) { - struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + struct ureg_program *ureg = ureg_create(PIPE_SHADER_FRAGMENT); if (!ureg) return NULL; @@ -517,7 +517,7 @@ util_make_fragment_cloneinput_shader(struct pipe_context *pipe, int num_cbufs, assert(num_cbufs <= PIPE_MAX_COLOR_BUFS); - ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT ); + ureg = ureg_create( PIPE_SHADER_FRAGMENT ); if (!ureg) return NULL; @@ -688,7 +688,7 @@ util_make_fs_msaa_resolve(struct pipe_context *pipe, struct ureg_dst out, tmp_sum, tmp_coord, tmp; int i; - ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + ureg = ureg_create(PIPE_SHADER_FRAGMENT); if (!ureg) return NULL; @@ -749,7 +749,7 @@ util_make_fs_msaa_resolve_bilinear(struct pipe_context *pipe, struct ureg_dst tmp_coord[4], tmp_sum[4]; int i, c; - ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + ureg = ureg_create(PIPE_SHADER_FRAGMENT); if (!ureg) return NULL; @@ -848,7 +848,7 @@ util_make_geometry_passthrough_shader(struct pipe_context *pipe, unsigned i; - ureg = ureg_create(TGSI_PROCESSOR_GEOMETRY); + ureg = ureg_create(PIPE_SHADER_GEOMETRY); if (!ureg) return NULL; diff --git a/src/gallium/auxiliary/vl/vl_compositor.c b/src/gallium/auxiliary/vl/vl_compositor.c index 77688f0f99f..acb2f4f4b97 100644 --- a/src/gallium/auxiliary/vl/vl_compositor.c +++ b/src/gallium/auxiliary/vl/vl_compositor.c @@ -62,7 +62,7 @@ create_vert_shader(struct vl_compositor *c) struct ureg_dst o_vpos, o_vtex, o_color; struct ureg_dst o_vtop, o_vbottom; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return false; @@ -136,7 +136,7 @@ create_frag_shader_video_buffer(struct vl_compositor *c) struct ureg_dst fragment; unsigned i; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return false; @@ -180,7 +180,7 @@ create_frag_shader_weave(struct vl_compositor *c) struct ureg_dst o_fragment; unsigned i, j; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return false; @@ -274,7 +274,7 @@ create_frag_shader_palette(struct vl_compositor *c, bool include_cc) struct ureg_dst fragment; unsigned i; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return false; @@ -318,7 +318,7 @@ create_frag_shader_rgba(struct vl_compositor *c) struct ureg_src tc, color, sampler; struct ureg_dst texel, fragment; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return false; diff --git a/src/gallium/auxiliary/vl/vl_deint_filter.c b/src/gallium/auxiliary/vl/vl_deint_filter.c index 9e782e531bf..cf260092002 100644 --- a/src/gallium/auxiliary/vl/vl_deint_filter.c +++ b/src/gallium/auxiliary/vl/vl_deint_filter.c @@ -67,7 +67,7 @@ create_vert_shader(struct vl_deint_filter *filter) struct ureg_src i_vpos; struct ureg_dst o_vpos, o_vtex; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -92,7 +92,7 @@ create_copy_frag_shader(struct vl_deint_filter *filter, unsigned field) struct ureg_dst o_fragment; struct ureg_dst t_tex; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) { return NULL; } @@ -136,7 +136,7 @@ create_deint_frag_shader(struct vl_deint_filter *filter, unsigned field, struct ureg_dst t_a, t_b; struct ureg_dst t_weave, t_linear; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) { return NULL; } diff --git a/src/gallium/auxiliary/vl/vl_idct.c b/src/gallium/auxiliary/vl/vl_idct.c index 948a5a403d7..deb97218545 100644 --- a/src/gallium/auxiliary/vl/vl_idct.c +++ b/src/gallium/auxiliary/vl/vl_idct.c @@ -148,7 +148,7 @@ create_mismatch_vert_shader(struct vl_idct *idct) struct ureg_dst t_tex; struct ureg_dst o_vpos, o_addr[2]; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -200,7 +200,7 @@ create_mismatch_frag_shader(struct vl_idct *idct) unsigned i; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return NULL; @@ -264,7 +264,7 @@ create_stage1_vert_shader(struct vl_idct *idct) struct ureg_dst t_tex, t_start; struct ureg_dst o_vpos, o_l_addr[2], o_r_addr[2]; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -329,7 +329,7 @@ create_stage1_frag_shader(struct vl_idct *idct) int i, j; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return NULL; diff --git a/src/gallium/auxiliary/vl/vl_matrix_filter.c b/src/gallium/auxiliary/vl/vl_matrix_filter.c index 52ce4540122..e6d91326ad0 100644 --- a/src/gallium/auxiliary/vl/vl_matrix_filter.c +++ b/src/gallium/auxiliary/vl/vl_matrix_filter.c @@ -52,7 +52,7 @@ create_vert_shader(struct vl_matrix_filter *filter) struct ureg_src i_vpos; struct ureg_dst o_vpos, o_vtex; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -87,7 +87,7 @@ create_frag_shader(struct vl_matrix_filter *filter, unsigned num_offsets, bool first; int i; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) { FREE(t_array); return NULL; diff --git a/src/gallium/auxiliary/vl/vl_mc.c b/src/gallium/auxiliary/vl/vl_mc.c index eb703a90445..a202fac54b0 100644 --- a/src/gallium/auxiliary/vl/vl_mc.c +++ b/src/gallium/auxiliary/vl/vl_mc.c @@ -112,7 +112,7 @@ create_ref_vert_shader(struct vl_mc *r) struct ureg_dst o_vmv[2]; unsigned i; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -169,7 +169,7 @@ create_ref_frag_shader(struct vl_mc *r) struct ureg_dst fragment; unsigned label; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return NULL; @@ -241,7 +241,7 @@ create_ycbcr_vert_shader(struct vl_mc *r, vl_mc_ycbcr_vert_shader vs_callback, v unsigned label; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -320,7 +320,7 @@ create_ycbcr_frag_shader(struct vl_mc *r, float scale, bool invert, struct ureg_dst fragment; unsigned label; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return NULL; diff --git a/src/gallium/auxiliary/vl/vl_median_filter.c b/src/gallium/auxiliary/vl/vl_median_filter.c index aa9a6b26485..3d022ef9355 100644 --- a/src/gallium/auxiliary/vl/vl_median_filter.c +++ b/src/gallium/auxiliary/vl/vl_median_filter.c @@ -50,7 +50,7 @@ create_vert_shader(struct vl_median_filter *filter) struct ureg_src i_vpos; struct ureg_dst o_vpos, o_vtex; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -93,13 +93,13 @@ create_frag_shader(struct vl_median_filter *filter, } if (num_offsets > screen->get_shader_param( - screen, TGSI_PROCESSOR_FRAGMENT, PIPE_SHADER_CAP_MAX_TEMPS)) { + screen, PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_MAX_TEMPS)) { FREE(t_array); return NULL; } - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) { FREE(t_array); return NULL; diff --git a/src/gallium/auxiliary/vl/vl_zscan.c b/src/gallium/auxiliary/vl/vl_zscan.c index 5241471f516..5ff442087d4 100644 --- a/src/gallium/auxiliary/vl/vl_zscan.c +++ b/src/gallium/auxiliary/vl/vl_zscan.c @@ -109,7 +109,7 @@ create_vert_shader(struct vl_zscan *zscan) signed i; - shader = ureg_create(TGSI_PROCESSOR_VERTEX); + shader = ureg_create(PIPE_SHADER_VERTEX); if (!shader) return NULL; @@ -186,7 +186,7 @@ create_frag_shader(struct vl_zscan *zscan) unsigned i; - shader = ureg_create(TGSI_PROCESSOR_FRAGMENT); + shader = ureg_create(PIPE_SHADER_FRAGMENT); if (!shader) return NULL; diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c index b48fb4659cd..6829544d354 100644 --- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c +++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c @@ -167,7 +167,7 @@ compile_init(struct fd2_compile_context *ctx, struct fd_program_stateobj *prog, ctx->output_export_idx[decl->Range.First] = semantic_idx(&decl->Semantic); - if (ctx->type == TGSI_PROCESSOR_VERTEX) { + if (ctx->type == PIPE_SHADER_VERTEX) { switch (name) { case TGSI_SEMANTIC_POSITION: ctx->position = ctx->num_regs[TGSI_FILE_OUTPUT]; @@ -307,7 +307,7 @@ static unsigned get_temp_gpr(struct fd2_compile_context *ctx, int idx) { unsigned num = idx + ctx->num_regs[TGSI_FILE_INPUT]; - if (ctx->type == TGSI_PROCESSOR_VERTEX) + if (ctx->type == PIPE_SHADER_VERTEX) num++; return num; } @@ -322,7 +322,7 @@ add_dst_reg(struct fd2_compile_context *ctx, struct ir2_instruction *alu, switch (dst->File) { case TGSI_FILE_OUTPUT: flags |= IR2_REG_EXPORT; - if (ctx->type == TGSI_PROCESSOR_VERTEX) { + if (ctx->type == PIPE_SHADER_VERTEX) { if (dst->Index == ctx->position) { num = 62; } else if (dst->Index == ctx->psize) { @@ -370,7 +370,7 @@ add_src_reg(struct fd2_compile_context *ctx, struct ir2_instruction *alu, flags |= IR2_REG_CONST; break; case TGSI_FILE_INPUT: - if (ctx->type == TGSI_PROCESSOR_VERTEX) { + if (ctx->type == PIPE_SHADER_VERTEX) { num = src->Index + 1; } else { num = export_linkage(ctx, @@ -1162,9 +1162,9 @@ fd2_compile_shader(struct fd_program_stateobj *prog, if (compile_init(&ctx, prog, so) != TGSI_PARSE_OK) return -1; - if (ctx.type == TGSI_PROCESSOR_VERTEX) { + if (ctx.type == PIPE_SHADER_VERTEX) { compile_vtx_fetch(&ctx); - } else if (ctx.type == TGSI_PROCESSOR_FRAGMENT) { + } else if (ctx.type == PIPE_SHADER_FRAGMENT) { prog->num_exports = 0; memset(prog->export_linkage, 0xff, sizeof(prog->export_linkage)); diff --git a/src/gallium/drivers/freedreno/freedreno_program.c b/src/gallium/drivers/freedreno/freedreno_program.c index e6a647852a3..9c51119d371 100644 --- a/src/gallium/drivers/freedreno/freedreno_program.c +++ b/src/gallium/drivers/freedreno/freedreno_program.c @@ -100,7 +100,7 @@ fd_prog_blit(struct pipe_context *pctx, int rts, bool depth) debug_assert(rts <= MAX_RENDER_TARGETS); - ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + ureg = ureg_create(PIPE_SHADER_FRAGMENT); if (!ureg) return NULL; diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c index 7ae4e94f0b3..027673afe1c 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c @@ -241,13 +241,13 @@ int main(int argc, char **argv) tgsi_parse_init(&parse, toks); switch (parse.FullHeader.Processor.Processor) { - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: s.type = v.type = SHADER_FRAGMENT; break; - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: s.type = v.type = SHADER_VERTEX; break; - case TGSI_PROCESSOR_COMPUTE: + case PIPE_SHADER_COMPUTE: s.type = v.type = SHADER_COMPUTE; break; } diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c index a284f27c366..61dec3f7be5 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c @@ -900,7 +900,7 @@ nv50_blitter_make_fp(struct pipe_context *pipe, mode != NV50_BLIT_MODE_XS) cvt_un8 = true; - ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + ureg = ureg_create(PIPE_SHADER_FRAGMENT); if (!ureg) return NULL; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c index d3024f9fa06..0f66e2a0bbd 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c @@ -848,7 +848,7 @@ nvc0_program_init_tcp_empty(struct nvc0_context *nvc0) { struct ureg_program *ureg; - ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL); + ureg = ureg_create(PIPE_SHADER_TESS_CTRL); if (!ureg) return; diff --git a/src/gallium/drivers/r300/r300_fs.c b/src/gallium/drivers/r300/r300_fs.c index 6a96e6720f7..7d76c06ed6b 100644 --- a/src/gallium/drivers/r300/r300_fs.c +++ b/src/gallium/drivers/r300/r300_fs.c @@ -220,7 +220,7 @@ static void r300_dummy_fragment_shader( struct ureg_src imm; /* Make a simple fragment shader which outputs (0, 0, 0, 1) */ - ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + ureg = ureg_create(PIPE_SHADER_FRAGMENT); out = ureg_DECL_output(ureg, TGSI_SEMANTIC_COLOR, 0); imm = ureg_imm4f(ureg, 0, 0, 0, 1); diff --git a/src/gallium/drivers/r300/r300_vs.c b/src/gallium/drivers/r300/r300_vs.c index 33612a322f7..62152714d20 100644 --- a/src/gallium/drivers/r300/r300_vs.c +++ b/src/gallium/drivers/r300/r300_vs.c @@ -187,7 +187,7 @@ static void r300_dummy_vertex_shader( /* Make a simple vertex shader which outputs (0, 0, 0, 1), * effectively rendering nothing. */ - ureg = ureg_create(TGSI_PROCESSOR_VERTEX); + ureg = ureg_create(PIPE_SHADER_VERTEX); dst = ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0); imm = ureg_imm4f(ureg, 0, 0, 0, 1); diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 2ba6003637e..c48d7586cbb 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -1690,7 +1690,7 @@ int r600_bytecode_build(struct r600_bytecode *bc) if (!bc->nstack) // If not 0, Stack_size already provided by llvm bc->nstack = bc->stack.max_entries; - if ((bc->type == TGSI_PROCESSOR_VERTEX || bc->type == TGSI_PROCESSOR_TESS_EVAL || bc->type == TGSI_PROCESSOR_TESS_CTRL) && !bc->nstack) { + if ((bc->type == PIPE_SHADER_VERTEX || bc->type == PIPE_SHADER_TESS_EVAL || bc->type == PIPE_SHADER_TESS_CTRL) && !bc->nstack) { bc->nstack = 1; } diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 77658f53551..64b049a1ced 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -182,13 +182,13 @@ int r600_pipe_shader_create(struct pipe_context *ctx, R600_ERR("translation from TGSI failed !\n"); goto error; } - if (shader->shader.processor_type == TGSI_PROCESSOR_VERTEX) { + if (shader->shader.processor_type == PIPE_SHADER_VERTEX) { /* only disable for vertex shaders in tess paths */ if (key.vs.as_ls) use_sb = 0; } - use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_CTRL); - use_sb &= (shader->shader.processor_type != TGSI_PROCESSOR_TESS_EVAL); + use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_CTRL); + use_sb &= (shader->shader.processor_type != PIPE_SHADER_TESS_EVAL); /* disable SB for shaders using doubles */ use_sb &= !shader->shader.uses_doubles; @@ -234,16 +234,16 @@ int r600_pipe_shader_create(struct pipe_context *ctx, /* Build state. */ switch (shader->shader.processor_type) { - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: evergreen_update_hs_state(ctx, shader); break; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: if (key.tes.as_es) evergreen_update_es_state(ctx, shader); else evergreen_update_vs_state(ctx, shader); break; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: if (rctx->b.chip_class >= EVERGREEN) { evergreen_update_gs_state(ctx, shader); evergreen_update_vs_state(ctx, shader->gs_copy_shader); @@ -252,7 +252,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx, r600_update_vs_state(ctx, shader->gs_copy_shader); } break; - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: export_shader = key.vs.as_es; if (rctx->b.chip_class >= EVERGREEN) { if (key.vs.as_ls) @@ -268,7 +268,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx, r600_update_vs_state(ctx, shader); } break; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: if (rctx->b.chip_class >= EVERGREEN) { evergreen_update_ps_state(ctx, shader); } else { @@ -412,12 +412,12 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx) case TGSI_FILE_CONSTANT: break; case TGSI_FILE_INPUT: - if (ctx->type == TGSI_PROCESSOR_GEOMETRY || - ctx->type == TGSI_PROCESSOR_TESS_CTRL || - ctx->type == TGSI_PROCESSOR_TESS_EVAL) + if (ctx->type == PIPE_SHADER_GEOMETRY || + ctx->type == PIPE_SHADER_TESS_CTRL || + ctx->type == PIPE_SHADER_TESS_EVAL) break; case TGSI_FILE_OUTPUT: - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) + if (ctx->type == PIPE_SHADER_TESS_CTRL) break; default: R600_ERR("unsupported src %d (file %d, dimension %d)\n", j, @@ -429,7 +429,7 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx) } for (j = 0; j < i->Instruction.NumDstRegs; j++) { if (i->Dst[j].Register.Dimension) { - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) + if (ctx->type == PIPE_SHADER_TESS_CTRL) continue; R600_ERR("unsupported dst (dimension)\n"); return -EINVAL; @@ -864,7 +864,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx) ctx->shader->input[i].interpolate = d->Interp.Interpolate; ctx->shader->input[i].interpolate_location = d->Interp.Location; ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + d->Range.First + j; - if (ctx->type == TGSI_PROCESSOR_FRAGMENT) { + if (ctx->type == PIPE_SHADER_FRAGMENT) { ctx->shader->input[i].spi_sid = r600_spi_sid(&ctx->shader->input[i]); switch (ctx->shader->input[i].name) { case TGSI_SEMANTIC_FACE: @@ -889,7 +889,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx) if ((r = evergreen_interp_input(ctx, i))) return r; } - } else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) { + } else if (ctx->type == PIPE_SHADER_GEOMETRY) { /* FIXME probably skip inputs if they aren't passed in the ring */ ctx->shader->input[i].ring_offset = ctx->next_ring_offset; ctx->next_ring_offset += 16; @@ -908,9 +908,9 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx) ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + d->Range.First + j; ctx->shader->output[i].interpolate = d->Interp.Interpolate; ctx->shader->output[i].write_mask = d->Declaration.UsageMask; - if (ctx->type == TGSI_PROCESSOR_VERTEX || - ctx->type == TGSI_PROCESSOR_GEOMETRY || - ctx->type == TGSI_PROCESSOR_TESS_EVAL) { + if (ctx->type == PIPE_SHADER_VERTEX || + ctx->type == PIPE_SHADER_GEOMETRY || + ctx->type == PIPE_SHADER_TESS_EVAL) { ctx->shader->output[i].spi_sid = r600_spi_sid(&ctx->shader->output[i]); switch (d->Semantic.Name) { case TGSI_SEMANTIC_CLIPDIST: @@ -939,10 +939,10 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx) ctx->cv_output = i; break; } - if (ctx->type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx->type == PIPE_SHADER_GEOMETRY) { ctx->gs_out_ring_offset += 16; } - } else if (ctx->type == TGSI_PROCESSOR_FRAGMENT) { + } else if (ctx->type == PIPE_SHADER_FRAGMENT) { switch (d->Semantic.Name) { case TGSI_SEMANTIC_COLOR: ctx->shader->nr_ps_max_color_exports++; @@ -1342,7 +1342,7 @@ static void tgsi_src(struct r600_shader_ctx *ctx, r600_src->swizzle[2] = 0; r600_src->swizzle[3] = 0; r600_src->sel = 0; - } else if (ctx->type != TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) { + } else if (ctx->type != PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_INVOCATIONID) { r600_src->swizzle[0] = 3; r600_src->swizzle[1] = 3; r600_src->swizzle[2] = 3; @@ -1361,7 +1361,7 @@ static void tgsi_src(struct r600_shader_ctx *ctx, } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_TESSOUTER) { r600_src->sel = 2; } else if (ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_VERTICESIN) { - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) { + if (ctx->type == PIPE_SHADER_TESS_CTRL) { r600_src->sel = ctx->tess_input_info; r600_src->swizzle[0] = 2; r600_src->swizzle[1] = 2; @@ -1374,13 +1374,13 @@ static void tgsi_src(struct r600_shader_ctx *ctx, r600_src->swizzle[2] = 3; r600_src->swizzle[3] = 3; } - } else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) { + } else if (ctx->type == PIPE_SHADER_TESS_CTRL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) { r600_src->sel = 0; r600_src->swizzle[0] = 0; r600_src->swizzle[1] = 0; r600_src->swizzle[2] = 0; r600_src->swizzle[3] = 0; - } else if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) { + } else if (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->info.system_value_semantic_name[tgsi_src->Register.Index] == TGSI_SEMANTIC_PRIMID) { r600_src->sel = 0; r600_src->swizzle[0] = 3; r600_src->swizzle[1] = 3; @@ -1853,19 +1853,19 @@ static int tgsi_split_lds_inputs(struct r600_shader_ctx *ctx) for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { struct tgsi_full_src_register *src = &inst->Src[i]; - if (ctx->type == TGSI_PROCESSOR_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) { + if (ctx->type == PIPE_SHADER_TESS_EVAL && src->Register.File == TGSI_FILE_INPUT) { int treg = r600_get_temp(ctx); fetch_tes_input(ctx, src, treg); ctx->src[i].sel = treg; ctx->src[i].rel = 0; } - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) { + if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_INPUT) { int treg = r600_get_temp(ctx); fetch_tcs_input(ctx, src, treg); ctx->src[i].sel = treg; ctx->src[i].rel = 0; } - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) { + if (ctx->type == PIPE_SHADER_TESS_CTRL && src->Register.File == TGSI_FILE_OUTPUT) { int treg = r600_get_temp(ctx); fetch_tcs_output(ctx, src, treg); ctx->src[i].sel = treg; @@ -2158,7 +2158,7 @@ static int generate_gs_copy_shader(struct r600_context *rctx, ctx.shader = &cshader->shader; ctx.bc = &ctx.shader->bc; - ctx.type = ctx.bc->type = TGSI_PROCESSOR_VERTEX; + ctx.type = ctx.bc->type = PIPE_SHADER_VERTEX; r600_bytecode_init(ctx.bc, rctx->b.chip_class, rctx->b.family, rctx->screen->has_compressed_msaa_texturing); @@ -2954,7 +2954,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, ctx.bc->type = shader->processor_type; switch (ctx.type) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: shader->vs_as_gs_a = key.vs.as_gs_a; shader->vs_as_es = key.vs.as_es; shader->vs_as_ls = key.vs.as_ls; @@ -2963,21 +2963,21 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, if (shader->vs_as_ls) lds_outputs = true; break; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: ring_outputs = true; break; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: shader->tcs_prim_mode = key.tcs.prim_mode; lds_outputs = true; lds_inputs = true; break; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: shader->tes_as_es = key.tes.as_es; lds_inputs = true; if (shader->tes_as_es) ring_outputs = true; break; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: shader->two_side = key.ps.color_two_side; break; default: @@ -3030,23 +3030,23 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, ctx.file_offset[i] = 0; } - if (ctx.type == TGSI_PROCESSOR_VERTEX) { + if (ctx.type == PIPE_SHADER_VERTEX) { ctx.file_offset[TGSI_FILE_INPUT] = 1; r600_bytecode_add_cfinst(ctx.bc, CF_OP_CALL_FS); } - if (ctx.type == TGSI_PROCESSOR_FRAGMENT) { + if (ctx.type == PIPE_SHADER_FRAGMENT) { if (ctx.bc->chip_class >= EVERGREEN) ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx); else ctx.file_offset[TGSI_FILE_INPUT] = allocate_system_value_inputs(&ctx, ctx.file_offset[TGSI_FILE_INPUT]); } - if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == PIPE_SHADER_GEOMETRY) { /* FIXME 1 would be enough in some cases (3 or less input vertices) */ ctx.file_offset[TGSI_FILE_INPUT] = 2; } - if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) + if (ctx.type == PIPE_SHADER_TESS_CTRL) ctx.file_offset[TGSI_FILE_INPUT] = 1; - if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) { + if (ctx.type == PIPE_SHADER_TESS_EVAL) { bool add_tesscoord = false, add_tess_inout = false; ctx.file_offset[TGSI_FILE_INPUT] = 1; for (i = 0; i < PIPE_MAX_SHADER_INPUTS; i++) { @@ -3079,15 +3079,15 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, ctx.bc->index_reg[0] = ctx.bc->ar_reg + 1; ctx.bc->index_reg[1] = ctx.bc->ar_reg + 2; - if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) { + if (ctx.type == PIPE_SHADER_TESS_CTRL) { ctx.tess_input_info = ctx.bc->ar_reg + 3; ctx.tess_output_info = ctx.bc->ar_reg + 4; ctx.temp_reg = ctx.bc->ar_reg + 5; - } else if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) { + } else if (ctx.type == PIPE_SHADER_TESS_EVAL) { ctx.tess_input_info = 0; ctx.tess_output_info = ctx.bc->ar_reg + 3; ctx.temp_reg = ctx.bc->ar_reg + 4; - } else if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { + } else if (ctx.type == PIPE_SHADER_GEOMETRY) { ctx.gs_export_gpr_tregs[0] = ctx.bc->ar_reg + 3; ctx.gs_export_gpr_tregs[1] = ctx.bc->ar_reg + 4; ctx.gs_export_gpr_tregs[2] = ctx.bc->ar_reg + 5; @@ -3126,7 +3126,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, if (shader->vs_as_gs_a) vs_add_primid_output(&ctx, key.vs.prim_id_out); - if (ctx.type == TGSI_PROCESSOR_TESS_EVAL) + if (ctx.type == PIPE_SHADER_TESS_EVAL) r600_fetch_tess_io_info(&ctx); while (!tgsi_parse_end_of_tokens(&ctx.parse)) { @@ -3240,7 +3240,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } } - if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == PIPE_SHADER_GEOMETRY) { struct r600_bytecode_alu alu; int r; @@ -3262,7 +3262,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } } - if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) + if (ctx.type == PIPE_SHADER_TESS_CTRL) r600_fetch_tess_io_info(&ctx); if (shader->two_side && ctx.colors_used) { @@ -3287,7 +3287,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, goto out_err; if ((r = tgsi_split_literal_constant(&ctx))) goto out_err; - if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == PIPE_SHADER_GEOMETRY) { if ((r = tgsi_split_gs_inputs(&ctx))) goto out_err; } else if (lds_inputs) { @@ -3304,7 +3304,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, if (r) goto out_err; - if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) { + if (ctx.type == PIPE_SHADER_TESS_CTRL) { r = r600_store_tcs_output(&ctx); if (r) goto out_err; @@ -3372,9 +3372,9 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, /* Add stream outputs. */ if (so.num_outputs) { bool emit = false; - if (!lds_outputs && !ring_outputs && ctx.type == TGSI_PROCESSOR_VERTEX) + if (!lds_outputs && !ring_outputs && ctx.type == PIPE_SHADER_VERTEX) emit = true; - if (!ring_outputs && ctx.type == TGSI_PROCESSOR_TESS_EVAL) + if (!ring_outputs && ctx.type == PIPE_SHADER_TESS_EVAL) emit = true; if (emit) emit_streamout(&ctx, &so, -1, NULL); @@ -3382,11 +3382,11 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, pipeshader->enabled_stream_buffers_mask = ctx.enabled_stream_buffers_mask; convert_edgeflag_to_int(&ctx); - if (ctx.type == TGSI_PROCESSOR_TESS_CTRL) + if (ctx.type == PIPE_SHADER_TESS_CTRL) r600_emit_tess_factor(&ctx); if (lds_outputs) { - if (ctx.type == TGSI_PROCESSOR_VERTEX) { + if (ctx.type == PIPE_SHADER_VERTEX) { if (ctx.shader->noutput) emit_lds_vs_writes(&ctx); } @@ -3415,8 +3415,8 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, output[j].type = -1; output[j].op = CF_OP_EXPORT; switch (ctx.type) { - case TGSI_PROCESSOR_VERTEX: - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_TESS_EVAL: switch (shader->output[i].name) { case TGSI_SEMANTIC_POSITION: output[j].array_base = 60; @@ -3506,7 +3506,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } break; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: if (shader->output[i].name == TGSI_SEMANTIC_COLOR) { /* never export more colors than the number of CBs */ if (shader->output[i].sid >= max_color_exports) { @@ -3560,7 +3560,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, goto out_err; } break; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: break; default: R600_ERR("unsupported processor type %d\n", ctx.type); @@ -3575,7 +3575,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } /* add fake position export */ - if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && pos_emitted == false) { + if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && pos_emitted == false) { memset(&output[j], 0, sizeof(struct r600_bytecode_output)); output[j].gpr = 0; output[j].elem_size = 3; @@ -3591,7 +3591,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } /* add fake param output for vertex shader if no param is exported */ - if ((ctx.type == TGSI_PROCESSOR_VERTEX || ctx.type == TGSI_PROCESSOR_TESS_EVAL) && next_param_base == 0) { + if ((ctx.type == PIPE_SHADER_VERTEX || ctx.type == PIPE_SHADER_TESS_EVAL) && next_param_base == 0) { memset(&output[j], 0, sizeof(struct r600_bytecode_output)); output[j].gpr = 0; output[j].elem_size = 3; @@ -3607,7 +3607,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, } /* add fake pixel export */ - if (ctx.type == TGSI_PROCESSOR_FRAGMENT && shader->nr_ps_color_exports == 0) { + if (ctx.type == PIPE_SHADER_FRAGMENT && shader->nr_ps_color_exports == 0) { memset(&output[j], 0, sizeof(struct r600_bytecode_output)); output[j].gpr = 0; output[j].elem_size = 3; @@ -3664,7 +3664,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, goto out_err; } - if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == PIPE_SHADER_GEOMETRY) { if ((r = generate_gs_copy_shader(rctx, pipeshader, &so))) return r; } @@ -3731,7 +3731,7 @@ static void tgsi_dst(struct r600_shader_ctx *ctx, if (inst->Instruction.Saturate) { r600_dst->clamp = 1; } - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) { + if (ctx->type == PIPE_SHADER_TESS_CTRL) { if (tgsi_dst->Register.File == TGSI_FILE_OUTPUT) { return; } @@ -6569,7 +6569,7 @@ static inline boolean tgsi_tex_src_requires_loading(struct r600_shader_ctx *ctx, inst->Src[index].Register.File != TGSI_FILE_INPUT && inst->Src[index].Register.File != TGSI_FILE_OUTPUT) || ctx->src[index].neg || ctx->src[index].abs || - (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == TGSI_PROCESSOR_GEOMETRY); + (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY); } static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx, diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 19c61ff4435..abc41e00846 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -1378,7 +1378,7 @@ static void r600_generate_fixed_func_tcs(struct r600_context *rctx) { struct ureg_src const0, const1; struct ureg_dst tessouter, tessinner; - struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL); + struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL); if (!ureg) return; /* if we get here, we're screwed */ diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp index 65aa801fb79..8124525bf4c 100644 --- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp +++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp @@ -56,18 +56,18 @@ int bc_parser::decode() { if (pshader) { switch (bc->type) { - case TGSI_PROCESSOR_FRAGMENT: t = TARGET_PS; break; - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_FRAGMENT: t = TARGET_PS; break; + case PIPE_SHADER_VERTEX: t = pshader->vs_as_ls ? TARGET_LS : (pshader->vs_as_es ? TARGET_ES : TARGET_VS); break; - case TGSI_PROCESSOR_GEOMETRY: t = TARGET_GS; break; - case TGSI_PROCESSOR_COMPUTE: t = TARGET_COMPUTE; break; - case TGSI_PROCESSOR_TESS_CTRL: t = TARGET_HS; break; - case TGSI_PROCESSOR_TESS_EVAL: t = pshader->tes_as_es ? TARGET_ES : TARGET_VS; break; + case PIPE_SHADER_GEOMETRY: t = TARGET_GS; break; + case PIPE_SHADER_COMPUTE: t = TARGET_COMPUTE; break; + case PIPE_SHADER_TESS_CTRL: t = TARGET_HS; break; + case PIPE_SHADER_TESS_EVAL: t = pshader->tes_as_es ? TARGET_ES : TARGET_VS; break; default: assert(!"unknown shader target"); return -1; break; } } else { - if (bc->type == TGSI_PROCESSOR_COMPUTE) + if (bc->type == PIPE_SHADER_COMPUTE) t = TARGET_COMPUTE; else t = TARGET_FETCH; diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index 9ed6da6a82b..929fecb9284 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -965,17 +965,17 @@ bool r600_can_dump_shader(struct r600_common_screen *rscreen, unsigned processor) { switch (processor) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: return (rscreen->debug_flags & DBG_VS) != 0; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: return (rscreen->debug_flags & DBG_TCS) != 0; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: return (rscreen->debug_flags & DBG_TES) != 0; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: return (rscreen->debug_flags & DBG_GS) != 0; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: return (rscreen->debug_flags & DBG_PS) != 0; - case TGSI_PROCESSOR_COMPUTE: + case PIPE_SHADER_COMPUTE: return (rscreen->debug_flags & DBG_CS) != 0; default: return false; diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c b/src/gallium/drivers/radeon/radeon_llvm_emit.c index d3f5ae3fab6..13633d33b04 100644 --- a/src/gallium/drivers/radeon/radeon_llvm_emit.c +++ b/src/gallium/drivers/radeon/radeon_llvm_emit.c @@ -81,21 +81,21 @@ void radeon_llvm_shader_type(LLVMValueRef F, unsigned type) enum radeon_llvm_calling_convention calling_conv; switch (type) { - case TGSI_PROCESSOR_VERTEX: - case TGSI_PROCESSOR_TESS_CTRL: - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_VERTEX: + case PIPE_SHADER_TESS_CTRL: + case PIPE_SHADER_TESS_EVAL: llvm_type = RADEON_LLVM_SHADER_VS; calling_conv = RADEON_LLVM_AMDGPU_VS; break; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: llvm_type = RADEON_LLVM_SHADER_GS; calling_conv = RADEON_LLVM_AMDGPU_GS; break; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: llvm_type = RADEON_LLVM_SHADER_PS; calling_conv = RADEON_LLVM_AMDGPU_PS; break; - case TGSI_PROCESSOR_COMPUTE: + case PIPE_SHADER_COMPUTE: llvm_type = RADEON_LLVM_SHADER_CS; calling_conv = RADEON_LLVM_AMDGPU_CS; break; diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index ea183701d05..e277c2f3914 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -70,7 +70,7 @@ struct si_shader_context struct si_shader *shader; struct si_screen *screen; - unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */ + unsigned type; /* PIPE_SHADER_* specifies the type of shader. */ bool is_gs_copy_shader; /* Whether to generate the optimized shader variant compiled as a whole @@ -240,10 +240,10 @@ static LLVMValueRef unpack_param(struct si_shader_context *ctx, static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx) { switch (ctx->type) { - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8); - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: return LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_tes_rel_patch_id); @@ -277,9 +277,9 @@ static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx) static LLVMValueRef get_tcs_in_patch_stride(struct si_shader_context *ctx) { - if (ctx->type == TGSI_PROCESSOR_VERTEX) + if (ctx->type == PIPE_SHADER_VERTEX) return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13); - else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) + else if (ctx->type == PIPE_SHADER_TESS_CTRL) return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13); else { assert(0); @@ -499,16 +499,16 @@ static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base, return bld_base->uint_bld.zero; switch (ctx->type) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: return LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_vs_prim_id); - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: return LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PATCH_ID); - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: return LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_tes_patch_id); - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: return LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIMITIVE_ID); default: @@ -1189,9 +1189,9 @@ static void declare_system_value( break; case TGSI_SEMANTIC_INVOCATIONID: - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) + if (ctx->type == PIPE_SHADER_TESS_CTRL) value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5); - else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) + else if (ctx->type == PIPE_SHADER_GEOMETRY) value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GS_INSTANCE_ID); else @@ -1490,7 +1490,7 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, /* Specify the target we are exporting */ args[3] = lp_build_const_int32(base->gallivm, target); - if (ctx->type == TGSI_PROCESSOR_FRAGMENT) { + if (ctx->type == PIPE_SHADER_FRAGMENT) { const union si_shader_key *key = &ctx->shader->key; unsigned col_formats = key->ps.epilog.spi_shader_col_format; int cbuf = target - V_008DFC_SQ_EXP_MRT; @@ -2374,7 +2374,7 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base) * an IF statement is added that clamps all colors if the constant * is true. */ - if (ctx->type == TGSI_PROCESSOR_VERTEX) { + if (ctx->type == PIPE_SHADER_VERTEX) { struct lp_build_if_state if_ctx; LLVMValueRef cond = NULL; LLVMValueRef addr, val; @@ -4748,7 +4748,7 @@ static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action, /* The real barrier instruction isn’t needed, because an entire patch * always fits into a single wave. */ - if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) { + if (ctx->type == PIPE_SHADER_TESS_CTRL) { emit_optimization_barrier(ctx); return; } @@ -4887,7 +4887,7 @@ static void create_function(struct si_shader_context *ctx) last_array_pointer = SI_PARAM_SHADER_BUFFERS; switch (ctx->type) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS); last_array_pointer = SI_PARAM_VERTEX_BUFFERS; params[SI_PARAM_BASE_VERTEX] = ctx->i32; @@ -4936,7 +4936,7 @@ static void create_function(struct si_shader_context *ctx) } break; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32; params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32; params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32; @@ -4958,7 +4958,7 @@ static void create_function(struct si_shader_context *ctx) } break; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32; params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32; num_params = SI_PARAM_TCS_OUT_LAYOUT+1; @@ -4983,7 +4983,7 @@ static void create_function(struct si_shader_context *ctx) returns[num_returns++] = ctx->f32; break; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: params[SI_PARAM_GS2VS_OFFSET] = ctx->i32; params[SI_PARAM_GS_WAVE_ID] = ctx->i32; last_sgpr = SI_PARAM_GS_WAVE_ID; @@ -5000,7 +5000,7 @@ static void create_function(struct si_shader_context *ctx) num_params = SI_PARAM_GS_INSTANCE_ID+1; break; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: params[SI_PARAM_ALPHA_REF] = ctx->f32; params[SI_PARAM_PRIM_MASK] = ctx->i32; last_sgpr = SI_PARAM_PRIM_MASK; @@ -5054,7 +5054,7 @@ static void create_function(struct si_shader_context *ctx) } break; - case TGSI_PROCESSOR_COMPUTE: + case PIPE_SHADER_COMPUTE: params[SI_PARAM_GRID_SIZE] = v3i32; params[SI_PARAM_BLOCK_ID] = v3i32; last_sgpr = SI_PARAM_BLOCK_ID; @@ -5073,7 +5073,7 @@ static void create_function(struct si_shader_context *ctx) num_params, last_array_pointer, last_sgpr); /* Reserve register locations for VGPR inputs the PS prolog may need. */ - if (ctx->type == TGSI_PROCESSOR_FRAGMENT && + if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->is_monolithic) { radeon_llvm_add_attribute(ctx->radeon_bld.main_fn, "InitialPSInputAddr", @@ -5085,7 +5085,7 @@ static void create_function(struct si_shader_context *ctx) S_0286D0_LINEAR_CENTROID_ENA(1) | S_0286D0_FRONT_FACE_ENA(1) | S_0286D0_POS_FIXED_PT_ENA(1)); - } else if (ctx->type == TGSI_PROCESSOR_COMPUTE) { + } else if (ctx->type == PIPE_SHADER_COMPUTE) { const unsigned *properties = shader->selector->info.properties; unsigned max_work_group_size = properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] * @@ -5108,7 +5108,7 @@ static void create_function(struct si_shader_context *ctx) /* Unused fragment shader inputs are eliminated by the compiler, * so we don't know yet how many there will be. */ - if (ctx->type != TGSI_PROCESSOR_FRAGMENT) + if (ctx->type != PIPE_SHADER_FRAGMENT) for (; i < num_params; ++i) shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4; @@ -5125,9 +5125,9 @@ static void create_function(struct si_shader_context *ctx) "ddxy_lds", LOCAL_ADDR_SPACE); - if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) || - ctx->type == TGSI_PROCESSOR_TESS_CTRL || - ctx->type == TGSI_PROCESSOR_TESS_EVAL) + if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) || + ctx->type == PIPE_SHADER_TESS_CTRL || + ctx->type == PIPE_SHADER_TESS_EVAL) declare_tess_lds(ctx); } @@ -5246,10 +5246,10 @@ static void preload_streamout_buffers(struct si_shader_context *ctx) /* Streamout can only be used if the shader is compiled as VS. */ if (!ctx->shader->selector->so.num_outputs || - (ctx->type == TGSI_PROCESSOR_VERTEX && + (ctx->type == PIPE_SHADER_VERTEX && (ctx->shader->key.vs.as_es || ctx->shader->key.vs.as_ls)) || - (ctx->type == TGSI_PROCESSOR_TESS_EVAL && + (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->shader->key.tes.as_es)) return; @@ -5279,13 +5279,13 @@ static void preload_ring_buffers(struct si_shader_context *ctx) LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); - if ((ctx->type == TGSI_PROCESSOR_VERTEX && + if ((ctx->type == PIPE_SHADER_VERTEX && ctx->shader->key.vs.as_es) || - (ctx->type == TGSI_PROCESSOR_TESS_EVAL && + (ctx->type == PIPE_SHADER_TESS_EVAL && ctx->shader->key.tes.as_es) || - ctx->type == TGSI_PROCESSOR_GEOMETRY) { + ctx->type == PIPE_SHADER_GEOMETRY) { unsigned ring = - ctx->type == TGSI_PROCESSOR_GEOMETRY ? SI_GS_RING_ESGS + ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS : SI_ES_RING_ESGS; LLVMValueRef offset = lp_build_const_int32(gallivm, ring); @@ -5299,7 +5299,7 @@ static void preload_ring_buffers(struct si_shader_context *ctx) ctx->gsvs_ring[0] = build_indexed_load_const(ctx, buf_ptr, offset); } - if (ctx->type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx->type == PIPE_SHADER_GEOMETRY) { int i; for (i = 0; i < 4; i++) { LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i); @@ -5545,7 +5545,7 @@ static void si_shader_dump_stats(struct si_screen *sscreen, unsigned max_simd_waves = 10; /* Compute LDS usage for PS. */ - if (processor == TGSI_PROCESSOR_FRAGMENT) { + if (processor == PIPE_SHADER_FRAGMENT) { /* The minimum usage per wave is (num_inputs * 36). The maximum * usage is (num_inputs * 36 * 16). * We can get anything in between and it varies between waves. @@ -5576,7 +5576,7 @@ static void si_shader_dump_stats(struct si_screen *sscreen, if (file != stderr || r600_can_dump_shader(&sscreen->b, processor)) { - if (processor == TGSI_PROCESSOR_FRAGMENT) { + if (processor == PIPE_SHADER_FRAGMENT) { fprintf(file, "*** SHADER CONFIG ***\n" "SPI_PS_INPUT_ADDR = 0x%04x\n" "SPI_PS_INPUT_ENA = 0x%04x\n", @@ -5608,28 +5608,28 @@ static const char *si_get_shader_name(struct si_shader *shader, unsigned processor) { switch (processor) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: if (shader->key.vs.as_es) return "Vertex Shader as ES"; else if (shader->key.vs.as_ls) return "Vertex Shader as LS"; else return "Vertex Shader as VS"; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: return "Tessellation Control Shader"; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: if (shader->key.tes.as_es) return "Tessellation Evaluation Shader as ES"; else return "Tessellation Evaluation Shader as VS"; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: if (shader->gs_copy_shader == NULL) return "GS Copy Shader as VS"; else return "Geometry Shader"; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: return "Pixel Shader"; - case TGSI_PROCESSOR_COMPUTE: + case PIPE_SHADER_COMPUTE: return "Compute Shader"; default: return "Unknown Shader"; @@ -5718,10 +5718,10 @@ int si_compile_llvm(struct si_screen *sscreen, * concatenated. */ if (binary->rodata_size && - (processor == TGSI_PROCESSOR_VERTEX || - processor == TGSI_PROCESSOR_TESS_CTRL || - processor == TGSI_PROCESSOR_TESS_EVAL || - processor == TGSI_PROCESSOR_FRAGMENT)) { + (processor == PIPE_SHADER_VERTEX || + processor == PIPE_SHADER_TESS_CTRL || + processor == PIPE_SHADER_TESS_EVAL || + processor == PIPE_SHADER_FRAGMENT)) { fprintf(stderr, "radeonsi: The shader can't have rodata."); return -EINVAL; } @@ -5746,7 +5746,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0])); si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm); - ctx->type = TGSI_PROCESSOR_VERTEX; + ctx->type = PIPE_SHADER_VERTEX; ctx->is_gs_copy_shader = true; create_meta_data(ctx); @@ -5794,7 +5794,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, /* Dump LLVM IR before any optimization passes */ if (sscreen->b.debug_flags & DBG_PREOPT_IR && - r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY)) + r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY)) LLVMDumpModule(bld_base->base.gallivm->module); radeon_llvm_finalize_module(&ctx->radeon_bld); @@ -5802,13 +5802,13 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, r = si_compile_llvm(sscreen, &ctx->shader->binary, &ctx->shader->config, ctx->tm, bld_base->base.gallivm->module, - debug, TGSI_PROCESSOR_GEOMETRY, + debug, PIPE_SHADER_GEOMETRY, "GS Copy Shader"); if (!r) { - if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY)) + if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY)) fprintf(stderr, "GS Copy Shader:\n"); si_shader_dump(sscreen, ctx->shader, debug, - TGSI_PROCESSOR_GEOMETRY, stderr); + PIPE_SHADER_GEOMETRY, stderr); r = si_shader_binary_upload(sscreen, ctx->shader); } @@ -5998,7 +5998,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, ctx.radeon_bld.load_system_value = declare_system_value; switch (ctx.type) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: ctx.radeon_bld.load_input = declare_input_vs; if (shader->key.vs.as_ls) bld_base->emit_epilogue = si_llvm_emit_ls_epilogue; @@ -6007,31 +6007,31 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, else bld_base->emit_epilogue = si_llvm_emit_vs_epilogue; break; - case TGSI_PROCESSOR_TESS_CTRL: + case PIPE_SHADER_TESS_CTRL: bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs; bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs; bld_base->emit_store = store_output_tcs; bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue; break; - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_EVAL: bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes; if (shader->key.tes.as_es) bld_base->emit_epilogue = si_llvm_emit_es_epilogue; else bld_base->emit_epilogue = si_llvm_emit_vs_epilogue; break; - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs; bld_base->emit_epilogue = si_llvm_emit_gs_epilogue; break; - case TGSI_PROCESSOR_FRAGMENT: + case PIPE_SHADER_FRAGMENT: ctx.radeon_bld.load_input = declare_input_fs; if (is_monolithic) bld_base->emit_epilogue = si_llvm_emit_fs_epilogue; else bld_base->emit_epilogue = si_llvm_return_fs_outputs; break; - case TGSI_PROCESSOR_COMPUTE: + case PIPE_SHADER_COMPUTE: ctx.radeon_bld.declare_memory_region = declare_compute_memory; break; default: @@ -6056,7 +6056,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, SI_PARAM_POS_FIXED_PT); } - if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == PIPE_SHADER_GEOMETRY) { int i; for (i = 0; i < 4; i++) { ctx.gs_next_vertex[i] = @@ -6094,7 +6094,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, shader->info.num_input_sgprs += 1; /* scratch byte offset */ /* Calculate the number of fragment input VGPRs. */ - if (ctx.type == TGSI_PROCESSOR_FRAGMENT) { + if (ctx.type == PIPE_SHADER_FRAGMENT) { shader->info.num_input_vgprs = 0; shader->info.face_vgpr_index = -1; @@ -6134,7 +6134,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, shader->info.num_input_vgprs += 1; } - if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == PIPE_SHADER_GEOMETRY) { shader->gs_copy_shader = CALLOC_STRUCT(si_shader); shader->gs_copy_shader->selector = shader->selector; ctx.shader = shader->gs_copy_shader; @@ -6232,7 +6232,7 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen, bool status = true; si_init_shader_ctx(&ctx, sscreen, &shader, tm); - ctx.type = TGSI_PROCESSOR_VERTEX; + ctx.type = PIPE_SHADER_VERTEX; ctx.param_vertex_id = key->vs_prolog.num_input_sgprs; ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3; @@ -6340,7 +6340,7 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen, bool status = true; si_init_shader_ctx(&ctx, sscreen, NULL, tm); - ctx.type = TGSI_PROCESSOR_VERTEX; + ctx.type = PIPE_SHADER_VERTEX; /* Declare input VGPRs. */ num_params = key->vs_epilog.states.export_prim_id ? @@ -6498,7 +6498,7 @@ static bool si_compile_tcs_epilog(struct si_screen *sscreen, bool status = true; si_init_shader_ctx(&ctx, sscreen, &shader, tm); - ctx.type = TGSI_PROCESSOR_TESS_CTRL; + ctx.type = PIPE_SHADER_TESS_CTRL; shader.key.tcs.epilog = key->tcs_epilog.states; /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */ @@ -6588,7 +6588,7 @@ static bool si_compile_ps_prolog(struct si_screen *sscreen, bool status = true; si_init_shader_ctx(&ctx, sscreen, &shader, tm); - ctx.type = TGSI_PROCESSOR_FRAGMENT; + ctx.type = PIPE_SHADER_FRAGMENT; shader.key.ps.prolog = key->ps_prolog.states; /* Number of inputs + 8 color elements. */ @@ -6750,7 +6750,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen, bool status = true; si_init_shader_ctx(&ctx, sscreen, &shader, tm); - ctx.type = TGSI_PROCESSOR_FRAGMENT; + ctx.type = PIPE_SHADER_FRAGMENT; shader.key.ps.epilog = key->ps_epilog.states; /* Declare input SGPRs. */ diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 4fc079716a7..80247f7281a 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -999,20 +999,20 @@ static void si_parse_next_shader_property(const struct tgsi_shader_info *info, unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER]; switch (info->processor) { - case TGSI_PROCESSOR_VERTEX: + case PIPE_SHADER_VERTEX: switch (next_shader) { - case TGSI_PROCESSOR_GEOMETRY: + case PIPE_SHADER_GEOMETRY: key->vs.as_es = 1; break; - case TGSI_PROCESSOR_TESS_CTRL: - case TGSI_PROCESSOR_TESS_EVAL: + case PIPE_SHADER_TESS_CTRL: + case PIPE_SHADER_TESS_EVAL: key->vs.as_ls = 1; break; } break; - case TGSI_PROCESSOR_TESS_EVAL: - if (next_shader == TGSI_PROCESSOR_GEOMETRY) + case PIPE_SHADER_TESS_EVAL: + if (next_shader == PIPE_SHADER_GEOMETRY) key->tes.as_es = 1; break; } @@ -1805,7 +1805,7 @@ static void si_generate_fixed_func_tcs(struct si_context *sctx) { struct ureg_src outer, inner; struct ureg_dst tessouter, tessinner; - struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL); + struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL); if (!ureg) return; /* if we get here, we're screwed */ diff --git a/src/gallium/drivers/svga/svga_state_fs.c b/src/gallium/drivers/svga/svga_state_fs.c index bac91669be1..72d591bb1bb 100644 --- a/src/gallium/drivers/svga/svga_state_fs.c +++ b/src/gallium/drivers/svga/svga_state_fs.c @@ -63,7 +63,7 @@ get_dummy_fragment_shader(void) struct ureg_dst dst; unsigned num_tokens; - ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + ureg = ureg_create(PIPE_SHADER_FRAGMENT); if (!ureg) return NULL; diff --git a/src/gallium/drivers/svga/svga_state_vs.c b/src/gallium/drivers/svga/svga_state_vs.c index a103dab25fe..f46e6b3d4da 100644 --- a/src/gallium/drivers/svga/svga_state_vs.c +++ b/src/gallium/drivers/svga/svga_state_vs.c @@ -54,7 +54,7 @@ get_dummy_vertex_shader(void) struct ureg_dst dst; unsigned num_tokens; - ureg = ureg_create(TGSI_PROCESSOR_VERTEX); + ureg = ureg_create(PIPE_SHADER_VERTEX); if (!ureg) return NULL; @@ -273,7 +273,7 @@ compile_passthrough_vs(struct svga_context *svga, num_inputs = fs->base.info.num_inputs; - ureg = ureg_create(TGSI_PROCESSOR_VERTEX); + ureg = ureg_create(PIPE_SHADER_VERTEX); if (!ureg) return PIPE_ERROR_OUT_OF_MEMORY; diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h index d1b95f3600a..514b339da71 100644 --- a/src/gallium/include/pipe/p_shader_tokens.h +++ b/src/gallium/include/pipe/p_shader_tokens.h @@ -40,18 +40,9 @@ struct tgsi_header unsigned BodySize : 24; }; -enum { - TGSI_PROCESSOR_FRAGMENT, - TGSI_PROCESSOR_VERTEX, - TGSI_PROCESSOR_GEOMETRY, - TGSI_PROCESSOR_TESS_CTRL, - TGSI_PROCESSOR_TESS_EVAL, - TGSI_PROCESSOR_COMPUTE, -}; - struct tgsi_processor { - unsigned Processor : 4; /* TGSI_PROCESSOR_ */ + unsigned Processor : 4; /* PIPE_SHADER_ */ unsigned Padding : 28; }; diff --git a/src/gallium/state_trackers/nine/nine_ff.c b/src/gallium/state_trackers/nine/nine_ff.c index d5daabd6661..7b26c954d3f 100644 --- a/src/gallium/state_trackers/nine/nine_ff.c +++ b/src/gallium/state_trackers/nine/nine_ff.c @@ -328,7 +328,7 @@ static void * nine_ff_build_vs(struct NineDevice9 *device, struct vs_build_ctx *vs) { const struct nine_ff_vs_key *key = vs->key; - struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_VERTEX); + struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX); struct ureg_dst oPos, oCol[2], oPsz, oFog; struct ureg_dst rVtx, rNrm; struct ureg_dst r[8]; @@ -1213,7 +1213,7 @@ static void * nine_ff_build_ps(struct NineDevice9 *device, struct nine_ff_ps_key *key) { struct ps_build_ctx ps; - struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + struct ureg_program *ureg = ureg_create(PIPE_SHADER_FRAGMENT); struct ureg_dst oCol; unsigned i, s; const unsigned texcoord_sn = get_texcoord_sn(device->screen); diff --git a/src/gallium/state_trackers/nine/nine_shader.c b/src/gallium/state_trackers/nine/nine_shader.c index eb6479bb4d9..dc886baba53 100644 --- a/src/gallium/state_trackers/nine/nine_shader.c +++ b/src/gallium/state_trackers/nine/nine_shader.c @@ -452,7 +452,7 @@ struct shader_translator BYTE major; BYTE minor; } version; - unsigned processor; /* TGSI_PROCESSOR_VERTEX/FRAMGENT */ + unsigned processor; /* PIPE_SHADER_VERTEX/FRAMGENT */ unsigned num_constf_allowed; unsigned num_consti_allowed; unsigned num_constb_allowed; @@ -517,8 +517,8 @@ struct shader_translator int16_t op_info_map[D3DSIO_BREAKP + 1]; }; -#define IS_VS (tx->processor == TGSI_PROCESSOR_VERTEX) -#define IS_PS (tx->processor == TGSI_PROCESSOR_FRAGMENT) +#define IS_VS (tx->processor == PIPE_SHADER_VERTEX) +#define IS_PS (tx->processor == PIPE_SHADER_FRAGMENT) #define FAILURE_VOID(cond) if ((cond)) {tx->failure=1;return;} @@ -2857,7 +2857,7 @@ create_op_info_map(struct shader_translator *tx) for (i = 0; i < Elements(tx->op_info_map); ++i) tx->op_info_map[i] = -1; - if (tx->processor == TGSI_PROCESSOR_VERTEX) { + if (tx->processor == PIPE_SHADER_VERTEX) { for (i = 0; i < Elements(inst_table); ++i) { assert(inst_table[i].sio < Elements(tx->op_info_map)); if (inst_table[i].vert_version.min <= version && @@ -2928,8 +2928,8 @@ sm1_read_version(struct shader_translator *tx) tx->version.minor = D3DSHADER_VERSION_MINOR(tok); switch (tok >> 16) { - case NINED3D_SM1_VS: tx->processor = TGSI_PROCESSOR_VERTEX; break; - case NINED3D_SM1_PS: tx->processor = TGSI_PROCESSOR_FRAGMENT; break; + case NINED3D_SM1_VS: tx->processor = PIPE_SHADER_VERTEX; break; + case NINED3D_SM1_PS: tx->processor = PIPE_SHADER_FRAGMENT; break; default: DBG("Invalid shader type: %x\n", tok); tx->processor = ~0; @@ -3258,8 +3258,8 @@ static inline unsigned tgsi_processor_from_type(unsigned shader_type) { switch (shader_type) { - case PIPE_SHADER_VERTEX: return TGSI_PROCESSOR_VERTEX; - case PIPE_SHADER_FRAGMENT: return TGSI_PROCESSOR_FRAGMENT; + case PIPE_SHADER_VERTEX: return PIPE_SHADER_VERTEX; + case PIPE_SHADER_FRAGMENT: return PIPE_SHADER_FRAGMENT; default: return ~0; } @@ -3348,7 +3348,7 @@ nine_translate_shader(struct NineDevice9 *device, struct nine_shader_info *info) DBG("Shader type mismatch: %u / %u !\n", tx->processor, processor); goto out; } - DUMP("%s%u.%u\n", processor == TGSI_PROCESSOR_VERTEX ? "VS" : "PS", + DUMP("%s%u.%u\n", processor == PIPE_SHADER_VERTEX ? "VS" : "PS", tx->version.major, tx->version.minor); tx->ureg = ureg_create(processor); diff --git a/src/gallium/state_trackers/xa/xa_tgsi.c b/src/gallium/state_trackers/xa/xa_tgsi.c index a50393d7886..f3f665d34d2 100644 --- a/src/gallium/state_trackers/xa/xa_tgsi.c +++ b/src/gallium/state_trackers/xa/xa_tgsi.c @@ -271,7 +271,7 @@ create_vs(struct pipe_context *pipe, unsigned vs_traits) boolean is_yuv = (vs_traits & VS_YUV) != 0; unsigned input_slot = 0; - ureg = ureg_create(TGSI_PROCESSOR_VERTEX); + ureg = ureg_create(PIPE_SHADER_VERTEX); if (ureg == NULL) return 0; @@ -469,7 +469,7 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits) (void)print_fs_traits; #endif - ureg = ureg_create(TGSI_PROCESSOR_FRAGMENT); + ureg = ureg_create(PIPE_SHADER_FRAGMENT); if (ureg == NULL) return 0; |