winsys/amdgpu: Use amdgpu_winsys helper instead of open-coded casts

Cleanup to prevent breakage with the next change, no functional change
intended in this one.

Reviewed-by: Marek Olšák <[email protected]>
Tested-by: Pierre-Eric Pelloux-Prayer <[email protected]>

3 files changed, 8 insertions, 8 deletions

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 955edb3a670..024d6131621 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -743,7 +743,7 @@ static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type)
 static bool amdgpu_get_new_ib(struct radeon_winsys *ws, struct amdgpu_cs *cs,
                               enum ib_type ib_type)
 {
-   struct amdgpu_winsys *aws = (struct amdgpu_winsys*)ws;
+   struct amdgpu_winsys *aws = amdgpu_winsys(ws);
    /* Small IBs are better than big IBs, because the GPU goes idle quicker
     * and there is less waiting for buffers and fences. Proof:
     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 2f0d0f28fc1..aba365f0f49 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -66,7 +66,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
                                enum radeon_surf_mode mode,
                                struct radeon_surf *surf)
 {
-   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
    int r;
 
    r = amdgpu_surface_sanity(tex);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 23ae61e9963..cf1f79c0ec2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -125,7 +125,7 @@ static void do_winsys_deinit(struct amdgpu_winsys *ws)
 
 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 {
-   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
 
    if (ws->reserve_vmid)
       amdgpu_vm_unreserve_vmid(ws->dev, 0);
@@ -149,7 +149,7 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 static void amdgpu_winsys_query_info(struct radeon_winsys *rws,
                                      struct radeon_info *info)
 {
-   *info = ((struct amdgpu_winsys *)rws)->info;
+   *info = amdgpu_winsys(rws)->info;
 }
 
 static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
@@ -162,7 +162,7 @@ static bool amdgpu_cs_request_feature(struct radeon_cmdbuf *rcs,
 static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
                                    enum radeon_value_id value)
 {
-   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
    struct amdgpu_heap_info heap;
    uint64_t retval = 0;
 
@@ -228,7 +228,7 @@ static bool amdgpu_read_registers(struct radeon_winsys *rws,
                                   unsigned reg_offset,
                                   unsigned num_registers, uint32_t *out)
 {
-   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
 
    return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
                                    0xffffffff, 0, out) == 0;
@@ -246,7 +246,7 @@ static int compare_pointers(void *key1, void *key2)
 
 static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 {
-   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
    bool destroy;
 
    /* When the reference counter drops to zero, remove the device pointer
@@ -272,7 +272,7 @@ static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
 static void amdgpu_pin_threads_to_L3_cache(struct radeon_winsys *rws,
                                            unsigned cache)
 {
-   struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
 
    util_pin_thread_to_L3(ws->cs_queue.threads[0], cache,
                          util_cpu_caps.cores_per_L3);