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authorVincent Lejeune <[email protected]>2012-09-04 17:04:28 +0200
committerVincent Lejeune <[email protected]>2012-09-04 17:52:53 +0200
commitd9e135e18cb438aad4b0bdf89a7273d705549150 (patch)
tree8e10ccffb234dfc181b59026cdfe8026124b5fcf /src/gallium
parenta383142436a21403dd19abb25a654fc634770c74 (diff)
radeon/llvm: support setcc on f32
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeon/R600ISelLowering.cpp36
1 files changed, 27 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 016befab69f..7ad017871cb 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -47,7 +47,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
setOperationAction(ISD::SETCC, MVT::i32, Custom);
-
+ setOperationAction(ISD::SETCC, MVT::f32, Custom);
setSchedulingPreference(Sched::VLIW);
}
@@ -519,14 +519,32 @@ SDValue R600TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue CC = Op.getOperand(2);
DebugLoc DL = Op.getDebugLoc();
assert(Op.getValueType() == MVT::i32);
- Cond = DAG.getNode(
- ISD::SELECT_CC,
- Op.getDebugLoc(),
- MVT::i32,
- LHS, RHS,
- DAG.getConstant(-1, MVT::i32),
- DAG.getConstant(0, MVT::i32),
- CC);
+ if (LHS.getValueType() == MVT::i32) {
+ Cond = DAG.getNode(
+ ISD::SELECT_CC,
+ Op.getDebugLoc(),
+ MVT::i32,
+ LHS, RHS,
+ DAG.getConstant(-1, MVT::i32),
+ DAG.getConstant(0, MVT::i32),
+ CC);
+ } else if (LHS.getValueType() == MVT::f32) {
+ Cond = DAG.getNode(
+ ISD::SELECT_CC,
+ Op.getDebugLoc(),
+ MVT::f32,
+ LHS, RHS,
+ DAG.getConstantFP(1.0f, MVT::f32),
+ DAG.getConstantFP(0.0f, MVT::f32),
+ CC);
+ Cond = DAG.getNode(
+ ISD::FP_TO_SINT,
+ DL,
+ MVT::i32,
+ Cond);
+ } else {
+ assert(0 && "Not valid type for set_cc");
+ }
Cond = DAG.getNode(
ISD::AND,
DL,