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authorAlyssa Rosenzweig <[email protected]>2019-05-22 02:44:12 +0000
committerAlyssa Rosenzweig <[email protected]>2019-06-04 20:14:50 +0000
commitc1715b558ab3dad36b094a8b44c10e53482eae9e (patch)
tree0162bff4b7abfe6e679d89490fe7b0afdfb683ef /src/gallium
parent550be763fa0aa9e5a060866963bae216cb1b9db3 (diff)
panfrost/midgard: Set masks on ld_vary
These masks distinguish scalar/vec2/vec3 loads from the default vec4, which helps with assembly readability (since it's immediately obvious how many components are _actually_ affected, rather than doing mysterious things to an unknown number of unused components). Later in the series, this will enable smarter register allocation, as the unused components will not be interpreted abnormally. Signed-off-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Ryan Houdek <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/panfrost/midgard/midgard_compile.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index afa272e1e5c..516fb2f67f9 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1153,6 +1153,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
case nir_intrinsic_load_input:
offset = nir_intrinsic_base(instr);
+ unsigned nr_comp = nir_intrinsic_dest_components(instr);
bool direct = nir_src_is_const(instr->src[0]);
if (direct) {
@@ -1168,6 +1169,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
/* TODO: swizzle, mask */
midgard_instruction ins = m_ld_vary_32(reg, offset);
+ ins.load_store.mask = (1 << nr_comp) - 1;
midgard_varying_parameter p = {
.is_varying = 1,
@@ -1199,7 +1201,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
} else if (ctx->stage == MESA_SHADER_VERTEX) {
midgard_instruction ins = m_ld_attr_32(reg, offset);
ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */
- ins.load_store.mask = (1 << instr->num_components) - 1;
+ ins.load_store.mask = (1 << nr_comp) - 1;
emit_mir_instruction(ctx, ins);
} else {
DBG("Unknown load\n");