diff options
| author | Marek Olšák <[email protected]> | 2017-11-07 02:01:40 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-10-30 16:03:02 -0400 |
| commit | 26cb93e229e3db3850c813f5fa156303a684c880 (patch) | |
| tree | 83fe5fa35401cd9c85f437fd2435d31725fec551 /src/gallium | |
| parent | 0dea85928e09c01a4f5964a56d126ac43e568a2e (diff) | |
radeonsi: add support for Raven2 (v2)
v2: fix enabling primitive binning
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 10 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_binning.c | 1 |
3 files changed, 10 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 6118b8076f1..490a3714836 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1033,10 +1033,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, if (sscreen->debug_flags & DBG(DPBB)) { sscreen->dpbb_allowed = true; } else { - /* Only enable primitive binning on Raven by default. */ + /* Only enable primitive binning on APUs by default. */ /* TODO: Investigate if binning is profitable on Vega12. */ - sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN && - !(sscreen->debug_flags & DBG(NO_DPBB)); + sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) && + (sscreen->info.family == CHIP_RAVEN || + sscreen->info.family == CHIP_RAVEN2); } if (sscreen->debug_flags & DBG(DFSM)) { @@ -1063,7 +1064,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, !(sscreen->debug_flags & DBG(NO_RB_PLUS)) && (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA12 || - sscreen->info.family == CHIP_RAVEN); + sscreen->info.family == CHIP_RAVEN || + sscreen->info.family == CHIP_RAVEN2); } sscreen->dcc_msaa_allowed = diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 43d76d19916..0293bdfa791 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -120,7 +120,8 @@ static void si_emit_cb_render_state(struct si_context *sctx) SI_TRACKED_CB_DCC_CONTROL, S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) | S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) | - S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable)); + S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) | + S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->family == CHIP_RAVEN2)); } /* RB+ register settings. */ @@ -5100,6 +5101,7 @@ static void si_init_config(struct si_context *sctx) pc_lines = 4096; break; case CHIP_RAVEN: + case CHIP_RAVEN2: pc_lines = 1024; break; default: diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index 70c129242d1..3516e561282 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -407,6 +407,7 @@ void si_emit_dpbb_state(struct si_context *sctx) case CHIP_VEGA12: case CHIP_VEGA20: case CHIP_RAVEN: + case CHIP_RAVEN2: /* Tuned for Raven. Vega might need different values. */ context_states_per_bin = 5; persistent_states_per_bin = 31; |