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authorMarek Olšák <[email protected]>2017-02-10 01:15:21 +0100
committerMarek Olšák <[email protected]>2017-02-18 01:22:08 +0100
commit9b91e0b54cc26919b63d781200a2062c6d572afc (patch)
treec355a555055368092160b7e3d8be9e3b4184ab61 /src/gallium
parent2fb021b6205a393d82d5f3c2e15af624d79742f4 (diff)
radeonsi: allow unaligned vertex buffer offsets and strides on CIK-VI
So that we can disable u_vbuf for GL core profiles. This is a v2 of the previous VI-only patch. It requires SH_MEM_CONFIG.ALIGNMENT_MODE = UNALIGNED on CIK-VI. Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 2dc884a63cd..61bcd2c3654 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -360,9 +360,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
- case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_START_INSTANCE:
@@ -462,6 +459,15 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
+ case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
+ case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
+ case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
+ /* SI doesn't support unaligned loads.
+ * CIK needs DRM 2.50.0 on radeon. */
+ return sscreen->b.chip_class == SI ||
+ (sscreen->b.info.drm_major == 2 &&
+ sscreen->b.info.drm_minor < 50);
+
/* Unsupported features. */
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: