Merge remote-tracking branch 'origin/master' into pipe-video

52 files changed, 1887 insertions, 1123 deletions

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.c b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
index 4636371a0f5..cb6717d7f63 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
@@ -1055,7 +1055,7 @@ lp_build_sample_partial_offset(struct lp_build_context *bld,
       subcoord = LLVMBuildURem(builder, coord, block_width, "");
       coord    = LLVMBuildUDiv(builder, coord, block_width, "");
 #else
-      unsigned logbase2 = util_unsigned_logbase2(block_length);
+      unsigned logbase2 = util_logbase2(block_length);
       LLVMValueRef block_shift = lp_build_const_int_vec(bld->gallivm, bld->type, logbase2);
       LLVMValueRef block_mask = lp_build_const_int_vec(bld->gallivm, bld->type, block_length - 1);
       subcoord = LLVMBuildAnd(builder, coord, block_mask, "");
diff --git a/src/gallium/auxiliary/util/u_math.h b/src/gallium/auxiliary/util/u_math.h
index dad6a101fd7..2ecade5f7e4 100644
--- a/src/gallium/auxiliary/util/u_math.h
+++ b/src/gallium/auxiliary/util/u_math.h
@@ -413,22 +413,6 @@ unsigned ffs( unsigned u )
 #define ffs __builtin_ffs
 #endif
 
-#ifdef __MINGW32__
-#define ffs __builtin_ffs
-#endif
-
-
-/* Could also binary search for the highest bit.
- */
-static INLINE unsigned
-util_unsigned_logbase2(unsigned n)
-{
-   unsigned log2 = 0;
-   while (n >>= 1)
-      ++log2;
-   return log2;
-}
-
 
 /**
  * Return float bits.
diff --git a/src/gallium/auxiliary/util/u_vbuf_mgr.c b/src/gallium/auxiliary/util/u_vbuf_mgr.c
index dea2928f950..a034483ee5c 100644
--- a/src/gallium/auxiliary/util/u_vbuf_mgr.c
+++ b/src/gallium/auxiliary/util/u_vbuf_mgr.c
@@ -53,9 +53,11 @@ struct u_vbuf_mgr_elements {
    unsigned count;
    struct pipe_vertex_element ve[PIPE_MAX_ATTRIBS];
 
-   /* If (velem[i].src_format != real_format[i]), the vertex buffer
+   unsigned src_format_size[PIPE_MAX_ATTRIBS];
+
+   /* If (velem[i].src_format != native_format[i]), the vertex buffer
     * referenced by the vertex element cannot be used for rendering and
-    * its vertex data must be translated to real_format[i]. */
+    * its vertex data must be translated to native_format[i]. */
    enum pipe_format native_format[PIPE_MAX_ATTRIBS];
    unsigned native_format_size[PIPE_MAX_ATTRIBS];
 
@@ -353,6 +355,8 @@ u_vbuf_mgr_create_vertex_elements(struct u_vbuf_mgr *mgrb,
    for (i = 0; i < count; i++) {
       enum pipe_format format = ve->ve[i].src_format;
 
+      ve->src_format_size[i] = util_format_get_blocksize(format);
+
       /* Choose a native format.
        * For now we don't care about the alignment, that's going to
        * be sorted out later. */
@@ -460,7 +464,6 @@ void u_vbuf_mgr_set_vertex_buffers(struct u_vbuf_mgr *mgrb,
    struct u_vbuf_mgr_priv *mgr = (struct u_vbuf_mgr_priv*)mgrb;
    unsigned i;
 
-   mgr->b.max_index = ~0;
    mgr->any_user_vbs = FALSE;
    mgr->incompatible_vb_layout = FALSE;
 
@@ -483,23 +486,16 @@ void u_vbuf_mgr_set_vertex_buffers(struct u_vbuf_mgr *mgrb,
       pipe_resource_reference(&mgr->b.vertex_buffer[i].buffer, vb->buffer);
       pipe_resource_reference(&mgr->b.real_vertex_buffer[i], NULL);
 
-      if (u_vbuf_resource(vb->buffer)->user_ptr) {
-         mgr->any_user_vbs = TRUE;
+      if (!vb->buffer) {
          continue;
       }
 
-      pipe_resource_reference(&mgr->b.real_vertex_buffer[i], vb->buffer);
-
-      /* The stride of zero means we will be fetching only the first
-       * vertex, so don't care about max_index. */
-      if (!vb->stride) {
+      if (u_vbuf_resource(vb->buffer)->user_ptr) {
+         mgr->any_user_vbs = TRUE;
          continue;
       }
 
-      /* Update the maximum index. */
-      mgr->b.max_index =
-            MIN2(mgr->b.max_index,
-                 (vb->buffer->width0 - vb->buffer_offset) / vb->stride - 1);
+      pipe_resource_reference(&mgr->b.real_vertex_buffer[i], vb->buffer);
    }
 
    for (; i < mgr->b.nr_real_vertex_buffers; i++) {
@@ -519,7 +515,7 @@ static void u_vbuf_upload_buffers(struct u_vbuf_mgr_priv *mgr,
                                   unsigned instance_count,
                                   boolean *upload_flushed)
 {
-   int i, nr = mgr->ve->count;
+   unsigned i, nr = mgr->ve->count;
    unsigned count = max_index + 1 - min_index;
    boolean uploaded[PIPE_MAX_ATTRIBS] = {0};
 
@@ -562,6 +558,40 @@ static void u_vbuf_upload_buffers(struct u_vbuf_mgr_priv *mgr,
    }
 }
 
+static void u_vbuf_mgr_compute_max_index(struct u_vbuf_mgr_priv *mgr)
+{
+   unsigned i, nr = mgr->ve->count;
+
+   mgr->b.max_index = ~0;
+
+   for (i = 0; i < nr; i++) {
+      struct pipe_vertex_buffer *vb =
+            &mgr->b.vertex_buffer[mgr->ve->ve[i].vertex_buffer_index];
+      int unused;
+      unsigned max_index;
+
+      if (!vb->buffer ||
+          !vb->stride ||
+          u_vbuf_resource(vb->buffer)->user_ptr) {
+         continue;
+      }
+
+      /* How many bytes is unused after the last vertex.
+       * width0 may be "count*stride - unused" and we have to compensate
+       * for that when dividing by stride. */
+      unused = vb->stride -
+               (mgr->ve->ve[i].src_offset + mgr->ve->src_format_size[i]);
+      assert(unused >= 0);
+
+      /* Compute the maximum index for this vertex element. */
+      max_index =
+         (vb->buffer->width0 - vb->buffer_offset + (unsigned)unused) /
+         vb->stride - 1;
+
+      mgr->b.max_index = MIN2(mgr->b.max_index, max_index);
+   }
+}
+
 void u_vbuf_mgr_draw_begin(struct u_vbuf_mgr *mgrb,
                            const struct pipe_draw_info *info,
                            boolean *buffers_updated,
@@ -571,6 +601,8 @@ void u_vbuf_mgr_draw_begin(struct u_vbuf_mgr *mgrb,
    boolean bufs_updated = FALSE, upload_flushed = FALSE;
    int min_index, max_index;
 
+   u_vbuf_mgr_compute_max_index(mgr);
+
    min_index = info->min_index - info->index_bias;
    if (info->max_index == ~0) {
       max_index = mgr->b.max_index;
diff --git a/src/gallium/drivers/cell/spu/spu_vertex_shader.c b/src/gallium/drivers/cell/spu/spu_vertex_shader.c
index 3e9804bf8ee..d6febd36f41 100644
--- a/src/gallium/drivers/cell/spu/spu_vertex_shader.c
+++ b/src/gallium/drivers/cell/spu/spu_vertex_shader.c
@@ -188,7 +188,7 @@ run_vertex_program(struct spu_vs_context *draw,
 
 
 PIPE_ALIGN_VAR(16) unsigned char
-immediates[(sizeof(float) * 4 * TGSI_EXEC_NUM_IMMEDIATES) + 32]);
+immediates[(sizeof(float) * 4 * TGSI_EXEC_NUM_IMMEDIATES) + 32];
 
 
 void
diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c
index 0e427749636..da96b420f2c 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -167,7 +167,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap)
       return 0;
 
    default:
-      debug_printf("%s: Unkown cap %u.\n", __FUNCTION__, cap);
+      debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
       return 0;
    }
 }
@@ -218,7 +218,7 @@ i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_sha
       case PIPE_SHADER_CAP_SUBROUTINES:
          return 0;
       default:
-         debug_printf("%s: Unkown cap %u.\n", __FUNCTION__, cap);
+         debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
          return 0;
    }
 }
@@ -244,7 +244,7 @@ i915_get_paramf(struct pipe_screen *screen, enum pipe_cap cap)
       return 16.0;
 
    default:
-      debug_printf("%s: Unkown cap %u.\n", __FUNCTION__, cap);
+      debug_printf("%s: Unknown cap %u.\n", __FUNCTION__, cap);
       return 0;
    }
 }
diff --git a/src/gallium/drivers/llvmpipe/lp_rast_debug.c b/src/gallium/drivers/llvmpipe/lp_rast_debug.c
index 64ac616f629..03e67dc8177 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_debug.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast_debug.c
@@ -397,8 +397,8 @@ lp_debug_draw_bins_by_cmd_length( struct lp_scene *scene )
    for (y = 0; y < scene->tiles_y; y++) {
       for (x = 0; x < scene->tiles_x; x++) {
          const char *bits = " ...,-~:;=o+xaw*#XAWWWWWWWWWWWWWWWW";
-         int sz = lp_scene_bin_size(scene, x, y);
-         int sz2 = util_unsigned_logbase2(sz);
+         unsigned sz = lp_scene_bin_size(scene, x, y);
+         unsigned sz2 = util_logbase2(sz);
          debug_printf("%c", bits[MIN2(sz2,32)]);
       }
       debug_printf("\n");
diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c
index 4dad8599870..cc921d08666 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -89,6 +89,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TEXTURE_SHADOW_MAP:
    case PIPE_CAP_NPOT_TEXTURES:
    case PIPE_CAP_ANISOTROPIC_FILTER:
+      return 1;
    case PIPE_CAP_SEAMLESS_CUBE_MAP:
       return nv50_screen(pscreen)->tesla->grclass >= NVA0_3D;
    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
@@ -488,7 +489,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
    BEGIN_RING(chan, RING_3D(LOCAL_ADDRESS_HIGH), 3);
    OUT_RELOCh(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
    OUT_RELOCl(chan, screen->tls_bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
-   OUT_RING  (chan, util_unsigned_logbase2(tls_space / 8));
+   OUT_RING  (chan, util_logbase2(tls_space / 8));
 
    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16,
                         &screen->uniforms);
diff --git a/src/gallium/drivers/nv50/nv50_transfer.c b/src/gallium/drivers/nv50/nv50_transfer.c
index 74869774595..d9fb22aa673 100644
--- a/src/gallium/drivers/nv50/nv50_transfer.c
+++ b/src/gallium/drivers/nv50/nv50_transfer.c
@@ -209,6 +209,9 @@ nv50_miptree_transfer_new(struct pipe_context *pctx,
    uint32_t w, h, d, z, layer;
    int ret;
 
+   if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
+      return NULL;
+
    if (mt->layout_3d) {
       z = box->z;
       d = u_minify(res->depth0, level);
diff --git a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
index 7f5fbaff690..82a8397238d 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
@@ -1293,31 +1293,45 @@ nv_pass_cse(struct nv_pass *ctx, struct nv_basic_block *b)
  * neighbouring registers. CSE might have messed this up.
  * Just generate a MOV for each source to avoid conflicts if they're used in
  * multiple NV_OP_BIND at different positions.
+ *
+ * Add a dummy use of the pointer source of >= 8 byte loads after the load
+ * to prevent it from being assigned a register which overlaps the load's
+ * destination, which would produce random corruptions.
  */
 static int
-nv_pass_fix_bind(struct nv_pass *ctx, struct nv_basic_block *b)
+nv_pass_fixups(struct nv_pass *ctx, struct nv_basic_block *b)
 {
    struct nv_value *val;
-   struct nv_instruction *bnd, *nvi, *next;
+   struct nv_instruction *fix, *nvi, *next;
    int s;
 
-   for (bnd = b->entry; bnd; bnd = next) {
-      next = bnd->next;
-      if (bnd->opcode != NV_OP_BIND)
+   for (fix = b->entry; fix; fix = next) {
+      next = fix->next;
+
+      if (fix->opcode == NV_OP_LD) {
+         if (fix->indirect >= 0 && fix->src[0]->value->reg.size >= 8) {
+            nvi = nv_alloc_instruction(ctx->pc, NV_OP_UNDEF);
+            nv_reference(ctx->pc, nvi, 0, fix->src[fix->indirect]->value);
+
+            nvc0_insn_insert_after(fix, nvi);
+         }
          continue;
-      for (s = 0; s < 4 && bnd->src[s]; ++s) {
-         val = bnd->src[s]->value;
+      } else
+      if (fix->opcode == NV_OP_BIND) {
+         for (s = 0; s < 4 && fix->src[s]; ++s) {
+            val = fix->src[s]->value;
 
-         nvi = nv_alloc_instruction(ctx->pc, NV_OP_MOV);
-         nvi->def[0] = new_value_like(ctx->pc, val);
-         nvi->def[0]->insn = nvi;
-         nv_reference(ctx->pc, nvi, 0, val);
-         nv_reference(ctx->pc, bnd, s, nvi->def[0]);
+            nvi = nv_alloc_instruction(ctx->pc, NV_OP_MOV);
+            nvi->def[0] = new_value_like(ctx->pc, val);
+            nvi->def[0]->insn = nvi;
+            nv_reference(ctx->pc, nvi, 0, val);
+            nv_reference(ctx->pc, fix, s, nvi->def[0]);
 
-         nvc0_insn_insert_before(bnd, nvi);
+            nvc0_insn_insert_before(fix, nvi);
+         }
       }
    }
-   DESCEND_ARBITRARY(s, nv_pass_fix_bind);
+   DESCEND_ARBITRARY(s, nv_pass_fixups);
 
    return 0;
 }
@@ -1403,7 +1417,7 @@ nv_pc_pass0(struct nv_pc *pc, struct nv_basic_block *root)
       return ret;
 
    pc->pass_seq++;
-   ret = nv_pass_fix_bind(&pass, root);
+   ret = nv_pass_fixups(&pass, root);
 
    return ret;
 }
diff --git a/src/gallium/drivers/nvc0/nvc0_transfer.c b/src/gallium/drivers/nvc0/nvc0_transfer.c
index 7bbfe057e58..0509113e005 100644
--- a/src/gallium/drivers/nvc0/nvc0_transfer.c
+++ b/src/gallium/drivers/nvc0/nvc0_transfer.c
@@ -246,6 +246,9 @@ nvc0_miptree_transfer_new(struct pipe_context *pctx,
    uint32_t w, h, d, z, layer;
    int ret;
 
+   if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
+      return NULL;
+
    tx = CALLOC_STRUCT(nvc0_transfer);
    if (!tx)
       return NULL;
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index 4a97dfb9c25..78212029534 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -81,6 +81,12 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 		return 0; // TODO: implement depth clamp
 	case PIPE_CAP_PRIMITIVE_RESTART:
 		return 0; // TODO: implement primitive restart
+	case PIPE_CAP_ARRAY_TEXTURES:
+	case PIPE_CAP_TGSI_INSTANCEID:
+	case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
+	case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
+	case PIPE_CAP_SEAMLESS_CUBE_MAP:
+	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 	case PIPE_CAP_SHADER_STENCIL_EXPORT:
 		return 0;
 	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c
index 1217488bac7..4ec77df8fb7 100644
--- a/src/gallium/drivers/r300/r300_blit.c
+++ b/src/gallium/drivers/r300/r300_blit.c
@@ -113,7 +113,7 @@ static boolean r300_fast_zclear_allowed(struct r300_context *r300)
     struct pipe_framebuffer_state *fb =
         (struct pipe_framebuffer_state*)r300->fb_state.state;
 
-    return r300_resource(fb->zsbuf->texture)->tex.zmask_dwords[fb->zsbuf->u.tex.level];
+    return r300_resource(fb->zsbuf->texture)->tex.zmask_dwords[fb->zsbuf->u.tex.level] != 0;
 }
 
 static boolean r300_hiz_clear_allowed(struct r300_context *r300)
@@ -121,7 +121,7 @@ static boolean r300_hiz_clear_allowed(struct r300_context *r300)
     struct pipe_framebuffer_state *fb =
         (struct pipe_framebuffer_state*)r300->fb_state.state;
 
-    return r300_resource(fb->zsbuf->texture)->tex.hiz_dwords[fb->zsbuf->u.tex.level];
+    return r300_resource(fb->zsbuf->texture)->tex.hiz_dwords[fb->zsbuf->u.tex.level] != 0;
 }
 
 static uint32_t r300_depth_clear_value(enum pipe_format format,
@@ -206,23 +206,47 @@ static void r300_clear(struct pipe_context* pipe,
         (struct r300_hyperz_state*)r300->hyperz_state.state;
     uint32_t width = fb->width;
     uint32_t height = fb->height;
-    boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ);
     uint32_t hyperz_dcv = hyperz->zb_depthclearvalue;
 
     /* Enable fast Z clear.
      * The zbuffer must be in micro-tiled mode, otherwise it locks up. */
-    if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && can_hyperz) {
-        if (r300_fast_zclear_allowed(r300)) {
-            hyperz_dcv = hyperz->zb_depthclearvalue =
-                r300_depth_clear_value(fb->zsbuf->format, depth, stencil);
-
-            r300_mark_atom_dirty(r300, &r300->zmask_clear);
-            buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
-        }
-
-        if (r300_hiz_clear_allowed(r300)) {
-            r300->hiz_clear_value = r300_hiz_clear_value(depth);
-            r300_mark_atom_dirty(r300, &r300->hiz_clear);
+    if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
+        boolean zmask_clear, hiz_clear;
+
+        zmask_clear = r300_fast_zclear_allowed(r300);
+        hiz_clear = r300_hiz_clear_allowed(r300);
+
+        /* If we need Hyper-Z. */
+        if (zmask_clear || hiz_clear) {
+            r300->num_z_clears++;
+
+            /* Try to obtain the access to Hyper-Z buffers if we don't have one. */
+            if (!r300->hyperz_enabled) {
+                r300->hyperz_enabled =
+                    r300->rws->cs_request_feature(r300->cs,
+                                                RADEON_FID_HYPERZ_RAM_ACCESS,
+                                                TRUE);
+                if (r300->hyperz_enabled) {
+                   /* Need to emit HyperZ buffer regs for the first time. */
+                   r300_mark_fb_state_dirty(r300, R300_CHANGED_HYPERZ_FLAG);
+                }
+            }
+
+            /* Setup Hyper-Z clears. */
+            if (r300->hyperz_enabled) {
+                if (zmask_clear) {
+                    hyperz_dcv = hyperz->zb_depthclearvalue =
+                        r300_depth_clear_value(fb->zsbuf->format, depth, stencil);
+
+                    r300_mark_atom_dirty(r300, &r300->zmask_clear);
+                    buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
+                }
+
+                if (hiz_clear) {
+                    r300->hiz_clear_value = r300_hiz_clear_value(depth);
+                    r300_mark_atom_dirty(r300, &r300->hiz_clear);
+                }
+            }
         }
     }
 
@@ -323,7 +347,7 @@ static void r300_clear_depth_stencil(struct pipe_context *pipe,
     struct pipe_framebuffer_state *fb =
         (struct pipe_framebuffer_state*)r300->fb_state.state;
 
-    if (r300->zmask_in_use && !r300->hyperz_locked) {
+    if (r300->zmask_in_use && !r300->locked_zbuffer) {
         if (fb->zsbuf->texture == dst->texture) {
             r300_decompress_zmask(r300);
         }
@@ -341,7 +365,7 @@ void r300_decompress_zmask(struct r300_context *r300)
     struct pipe_framebuffer_state *fb =
         (struct pipe_framebuffer_state*)r300->fb_state.state;
 
-    if (!r300->zmask_in_use || r300->hyperz_locked)
+    if (!r300->zmask_in_use || r300->locked_zbuffer)
         return;
 
     r300->zmask_decompress = TRUE;
@@ -377,6 +401,8 @@ void r300_decompress_zmask_locked(struct r300_context *r300)
     r300_decompress_zmask_locked_unsafe(r300);
     r300->context.set_framebuffer_state(&r300->context, &saved_fb);
     util_unreference_framebuffer_state(&saved_fb);
+
+    pipe_surface_reference(&r300->locked_zbuffer, NULL);
 }
 
 /* Copy a block of pixels from one surface to another using HW. */
@@ -423,7 +449,7 @@ static void r300_resource_copy_region(struct pipe_context *pipe,
         return;
     }
 
-    if (r300->zmask_in_use && !r300->hyperz_locked) {
+    if (r300->zmask_in_use && !r300->locked_zbuffer) {
         if (fb->zsbuf->texture == src ||
             fb->zsbuf->texture == dst) {
             r300_decompress_zmask(r300);
diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index 15d1278c3bb..0554c40eef0 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -26,6 +26,7 @@
 #include "util/u_sampler.h"
 #include "util/u_simple_list.h"
 #include "util/u_upload_mgr.h"
+#include "os/os_time.h"
 
 #include "r300_cb.h"
 #include "r300_context.h"
@@ -95,6 +96,10 @@ static void r300_destroy_context(struct pipe_context* context)
 {
     struct r300_context* r300 = r300_context(context);
 
+    if (r300->cs && r300->hyperz_enabled) {
+        r300->rws->cs_request_feature(r300->cs, RADEON_FID_HYPERZ_RAM_ACCESS, FALSE);
+    }
+
     if (r300->blitter)
         util_blitter_destroy(r300->blitter);
     if (r300->draw)
@@ -167,8 +172,6 @@ static boolean r300_setup_atoms(struct r300_context* r300)
     boolean is_r500 = r300->screen->caps.is_r500;
     boolean has_tcl = r300->screen->caps.has_tcl;
     boolean drm_2_6_0 = r300->rws->get_value(r300->rws, RADEON_VID_DRM_2_6_0);
-    boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ);
-    boolean has_hiz_ram = r300->screen->caps.hiz_ram > 0;
 
     /* Create the actual atom list.
      *
@@ -219,13 +222,10 @@ static boolean r300_setup_atoms(struct r300_context* r300)
     /* TX. */
     R300_INIT_ATOM(texture_cache_inval, 2);
     R300_INIT_ATOM(textures_state, 0);
-    if (can_hyperz) {
-        /* HiZ Clear */
-        if (has_hiz_ram)
-            R300_INIT_ATOM(hiz_clear, 4);
-        /* zmask clear */
-        R300_INIT_ATOM(zmask_clear, 4);
-    }
+    /* HiZ Clear */
+    R300_INIT_ATOM(hiz_clear, r300->screen->caps.hiz_ram > 0 ? 4 : 0);
+    /* zmask clear */
+    R300_INIT_ATOM(zmask_clear, r300->screen->caps.zmask_ram > 0 ? 4 : 0);
     /* ZB (unpipelined), SU. */
     R300_INIT_ATOM(query_start, 4);
 
@@ -503,6 +503,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
                                                            &dsa);
     }
 
+    r300->hyperz_time_of_last_flush = os_time_get();
+
     /* Print driver info. */
 #ifdef DEBUG
     {
@@ -512,7 +514,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
         fprintf(stderr,
                 "r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
                 "r300: GART size: %d MB, VRAM size: %d MB\n"
-                "r300: AA compression: %s, Z compression: %s, HiZ: %s\n",
+                "r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
                 rws->get_value(rws, RADEON_VID_DRM_MAJOR),
                 rws->get_value(rws, RADEON_VID_DRM_MINOR),
                 rws->get_value(rws, RADEON_VID_DRM_PATCHLEVEL),
@@ -522,10 +524,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
                 rws->get_value(rws, RADEON_VID_R300_Z_PIPES),
                 rws->get_value(rws, RADEON_VID_GART_SIZE) >> 20,
                 rws->get_value(rws, RADEON_VID_VRAM_SIZE) >> 20,
-                rws->get_value(rws, RADEON_VID_CAN_AACOMPRESS) ? "YES" : "NO",
-                rws->get_value(rws, RADEON_VID_CAN_HYPERZ) &&
+                "YES", /* XXX really? */
                 r300->screen->caps.zmask_ram ? "YES" : "NO",
-                rws->get_value(rws, RADEON_VID_CAN_HYPERZ) &&
                 r300->screen->caps.hiz_ram ? "YES" : "NO");
     }
 
diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
index 8a0a54cf1e9..139dd210b8f 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -592,20 +592,6 @@ struct r300_context {
     boolean frag_clamp;
     /* Whether fast color clear is enabled. */
     boolean cbzb_clear;
-    /* Whether ZMASK is enabled. */
-    boolean zmask_in_use;
-    /* Whether ZMASK is being decompressed. */
-    boolean zmask_decompress;
-    /* Whether ZMASK/HIZ is locked, i.e. should be disabled and cannot be taken over. */
-    boolean hyperz_locked;
-    /* The zbuffer the ZMASK of which is locked. */
-    struct pipe_surface *locked_zbuffer;
-    /* Whether HIZ is enabled. */
-    boolean hiz_in_use;
-    /* HiZ function. Can be either MIN or MAX. */
-    enum r300_hiz_func hiz_func;
-    /* HiZ clear value. */
-    uint32_t hiz_clear_value;
     /* Whether fragment shader needs to be validated. */
     enum r300_fs_validity_status fs_status;
     /* Framebuffer multi-write. */
@@ -629,6 +615,21 @@ struct r300_context {
     int vertex_arrays_offset;
     int vertex_arrays_instance_id;
     boolean instancing_enabled;
+
+    /* Hyper-Z stats. */
+    boolean hyperz_enabled;     /* Whether it owns Hyper-Z access. */
+    int64_t hyperz_time_of_last_flush; /* Time of the last flush with Z clear. */
+    unsigned num_z_clears;      /* Since the last flush. */
+
+    /* ZMask state. */
+    boolean zmask_in_use;       /* Whether ZMASK is enabled. */
+    boolean zmask_decompress;   /* Whether ZMASK is being decompressed. */
+    struct pipe_surface *locked_zbuffer; /* Unbound zbuffer which still has data in ZMASK. */
+
+    /* HiZ state. */
+    boolean hiz_in_use;         /* Whether HIZ is enabled. */
+    enum r300_hiz_func hiz_func; /* HiZ function. Can be either MIN or MAX. */
+    uint32_t hiz_clear_value;   /* HiZ clear value. */
 };
 
 #define foreach_atom(r300, atom) \
diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index 62435c5e2e2..874037ed9fd 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -375,7 +375,6 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
     struct pipe_framebuffer_state* fb = (struct pipe_framebuffer_state*)state;
     struct r300_surface* surf;
     unsigned i;
-    boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ);
     uint32_t rb3d_cctl = 0;
 
     CS_LOCALS(r300);
@@ -432,7 +431,7 @@ void r300_emit_fb_state(struct r300_context* r300, unsigned size, void* state)
         OUT_CS_REG(R300_ZB_DEPTHPITCH, surf->pitch);
         OUT_CS_RELOC(surf);
 
-        if (can_hyperz) {
+        if (r300->hyperz_enabled) {
             /* HiZ RAM. */
             OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0);
             OUT_CS_REG(R300_ZB_HIZ_PITCH, surf->pitch_hiz);
diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c
index de7d77d608b..34f5419a864 100644
--- a/src/gallium/drivers/r300/r300_flush.c
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -27,17 +27,46 @@
 #include "util/u_simple_list.h"
 #include "util/u_upload_mgr.h"
 
+#include "os/os_time.h"
+
 #include "r300_context.h"
 #include "r300_cs.h"
 #include "r300_emit.h"
 
 
+static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags)
+{
+    struct r300_atom *atom;
+
+    r300_emit_hyperz_end(r300);
+    r300_emit_query_end(r300);
+    if (r300->screen->caps.is_r500)
+        r500_emit_index_bias(r300, 0);
+
+    r300->flush_counter++;
+    r300->rws->cs_flush(r300->cs, flags);
+    r300->dirty_hw = 0;
+
+    /* New kitchen sink, baby. */
+    foreach_atom(r300, atom) {
+        if (atom->state || atom->allow_null_state) {
+            r300_mark_atom_dirty(r300, atom);
+        }
+    }
+    r300->vertex_arrays_dirty = TRUE;
+
+    /* Unmark HWTCL state for SWTCL. */
+    if (!r300->screen->caps.has_tcl) {
+        r300->vs_state.dirty = FALSE;
+        r300->vs_constants.dirty = FALSE;
+    }
+}
+
 void r300_flush(struct pipe_context *pipe,
                 unsigned flags,
                 struct pipe_fence_handle **fence)
 {
     struct r300_context *r300 = r300_context(pipe);
-    struct r300_atom *atom;
     struct pb_buffer **rfence = (struct pb_buffer**)fence;
 
     if (r300->draw && !r300->draw_vbo_locked)
@@ -56,32 +85,11 @@ void r300_flush(struct pipe_context *pipe,
     }
 
     if (r300->dirty_hw) {
-        r300_emit_hyperz_end(r300);
-        r300_emit_query_end(r300);
-        if (r300->screen->caps.is_r500)
-            r500_emit_index_bias(r300, 0);
-
-        r300->flush_counter++;
-        r300->rws->cs_flush(r300->cs, flags);
-        r300->dirty_hw = 0;
-
-        /* New kitchen sink, baby. */
-        foreach_atom(r300, atom) {
-            if (atom->state || atom->allow_null_state) {
-                r300_mark_atom_dirty(r300, atom);
-            }
-        }
-        r300->vertex_arrays_dirty = TRUE;
-
-        /* Unmark HWTCL state for SWTCL. */
-        if (!r300->screen->caps.has_tcl) {
-            r300->vs_state.dirty = FALSE;
-            r300->vs_constants.dirty = FALSE;
-        }
+        r300_flush_and_cleanup(r300, flags);
     } else {
         if (rfence) {
             /* We have to create a fence object, but the command stream is empty
-             * and we cannot emit an empty CS. We must write some regs then. */
+             * and we cannot emit an empty CS. Let's write to some reg. */
             CS_LOCALS(r300);
             OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0);
             r300->rws->cs_flush(r300->cs, flags);
@@ -91,6 +99,32 @@ void r300_flush(struct pipe_context *pipe,
             r300->rws->cs_flush(r300->cs, flags);
         }
     }
+
+    /* Update Hyper-Z status. */
+    if (r300->num_z_clears) {
+        r300->hyperz_time_of_last_flush = os_time_get();
+    } else if (!r300->hyperz_time_of_last_flush > 2000000) {
+        /* 2 seconds without a Z clear pretty much means a dead context
+         * for HyperZ. */
+
+        r300->hiz_in_use = FALSE;
+
+        /* Decompress Z buffer. */
+        if (r300->zmask_in_use) {
+            if (r300->locked_zbuffer) {
+                r300_decompress_zmask_locked(r300);
+            } else {
+                r300_decompress_zmask(r300);
+            }
+
+            r300_flush_and_cleanup(r300, flags);
+        }
+
+        /* Release HyperZ. */
+        r300->rws->cs_request_feature(r300->cs, RADEON_FID_HYPERZ_RAM_ACCESS,
+                                      FALSE);
+    }
+    r300->num_z_clears = 0;
 }
 
 static void r300_flush_wrapped(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/r300/r300_hyperz.c b/src/gallium/drivers/r300/r300_hyperz.c
index ef330f34c9e..e946d61d0ed 100644
--- a/src/gallium/drivers/r300/r300_hyperz.c
+++ b/src/gallium/drivers/r300/r300_hyperz.c
@@ -43,16 +43,13 @@ static enum r300_hiz_func r300_get_hiz_func(struct r300_context *r300)
 {
     struct r300_dsa_state *dsa = r300->dsa_state.state;
 
-    if (!dsa->dsa.depth.enabled || !dsa->dsa.depth.writemask)
-        return HIZ_FUNC_NONE;
-
     switch (dsa->dsa.depth.func) {
     case PIPE_FUNC_NEVER:
     case PIPE_FUNC_EQUAL:
     case PIPE_FUNC_NOTEQUAL:
     case PIPE_FUNC_ALWAYS:
-        return HIZ_FUNC_NONE;
-
+    default:
+        /* Guess MAX for uncertain cases. */
     case PIPE_FUNC_LESS:
     case PIPE_FUNC_LEQUAL:
         return HIZ_FUNC_MAX;
@@ -60,10 +57,6 @@ static enum r300_hiz_func r300_get_hiz_func(struct r300_context *r300)
     case PIPE_FUNC_GREATER:
     case PIPE_FUNC_GEQUAL:
         return HIZ_FUNC_MIN;
-
-    default:
-        assert(0);
-        return HIZ_FUNC_NONE;
     }
 }
 
@@ -103,18 +96,21 @@ static boolean r300_dsa_stencil_op_not_keep(struct pipe_stencil_state *s)
                           s->zfail_op != PIPE_STENCIL_OP_KEEP);
 }
 
-static boolean r300_can_hiz(struct r300_context *r300)
+static boolean r300_hiz_allowed(struct r300_context *r300)
 {
     struct r300_dsa_state *dsa = r300->dsa_state.state;
     struct r300_screen *r300screen = r300->screen;
 
-    /* shader writes depth - no HiZ */
-    if (r300_fragment_shader_writes_depth(r300_fs(r300))) /* (5) */
+    if (r300_fragment_shader_writes_depth(r300_fs(r300)))
         return FALSE;
 
     if (r300->query_current)
         return FALSE;
 
+    /* If the depth function is inverted, HiZ must be disabled. */
+    if (!r300_is_hiz_func_valid(r300))
+        return FALSE;
+
     /* if stencil fail/zfail op is not KEEP */
     if (r300_dsa_stencil_op_not_keep(&dsa->dsa.stencil[0]) ||
         r300_dsa_stencil_op_not_keep(&dsa->dsa.stencil[1]))
@@ -138,6 +134,7 @@ static void r300_update_hyperz(struct r300_context* r300)
         (struct r300_hyperz_state*)r300->hyperz_state.state;
     struct pipe_framebuffer_state *fb =
         (struct pipe_framebuffer_state*)r300->fb_state.state;
+    struct r300_dsa_state *dsa = r300->dsa_state.state;
     struct r300_resource *zstex =
             fb->zsbuf ? r300_resource(fb->zsbuf->texture) : NULL;
 
@@ -151,55 +148,70 @@ static void r300_update_hyperz(struct r300_context* r300)
         return;
     }
 
-    if (!zstex ||
-        !r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ))
+    if (!zstex || !r300->hyperz_enabled)
         return;
 
-    /* Zbuffer compression. */
-    if (r300->zmask_in_use && !r300->hyperz_locked) {
+    /* Set the size of ZMASK tiles. */
+    if (zstex->tex.zcomp8x8[fb->zsbuf->u.tex.level]) {
+        z->gb_z_peq_config |= R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8;
+    }
+
+    /* R500-specific features and optimizations. */
+    if (r300->screen->caps.is_r500) {
+        z->zb_bw_cntl |= R500_PEQ_PACKING_ENABLE |
+                         R500_COVERED_PTR_MASKING_ENABLE;
+    }
+
+    /* Setup decompression if needed. No other HyperZ setting is required. */
+    if (r300->zmask_decompress) {
         z->zb_bw_cntl |= R300_FAST_FILL_ENABLE |
-                         /*R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE |*/
                          R300_RD_COMP_ENABLE;
+        return;
+    }
 
-        if (!r300->zmask_decompress) {
-            z->zb_bw_cntl |= R300_WR_COMP_ENABLE;
-        }
+    /* Do not set anything if depth and stencil tests are off. */
+    if (!dsa->dsa.depth.enabled &&
+        !dsa->dsa.stencil[0].enabled &&
+        !dsa->dsa.stencil[1].enabled) {
+        assert(!dsa->dsa.depth.writemask);
+        return;
     }
 
-    if (zstex->tex.zcomp8x8[fb->zsbuf->u.tex.level]) {
-        z->gb_z_peq_config |= R300_GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8;
+    /* Zbuffer compression. */
+    if (r300->zmask_in_use && !r300->locked_zbuffer) {
+        z->zb_bw_cntl |= R300_FAST_FILL_ENABLE |
+                         R300_RD_COMP_ENABLE |
+                         R300_WR_COMP_ENABLE;
     }
 
     /* HiZ. */
-    if (r300->hiz_in_use && !r300->hyperz_locked) {
+    if (r300->hiz_in_use && !r300->locked_zbuffer) {
+        /* HiZ cannot be used under some circumstances. */
+        if (!r300_hiz_allowed(r300)) {
+            /* If writemask is disabled, the HiZ memory will not be changed,
+             * so we can keep its content for later. */
+            if (dsa->dsa.depth.writemask) {
+                r300->hiz_in_use = FALSE;
+            }
+            return;
+        }
+
         /* Set the HiZ function if needed. */
         if (r300->hiz_func == HIZ_FUNC_NONE) {
             r300->hiz_func = r300_get_hiz_func(r300);
         }
 
-        /* If the depth function is inverted, HiZ must be disabled. */
-        if (!r300_is_hiz_func_valid(r300)) {
-            r300->hiz_in_use = FALSE;
-        } else if (r300_can_hiz(r300)) {
-            /* Setup the HiZ bits. */
-            z->zb_bw_cntl |=
-                R300_HIZ_ENABLE |
+        /* Setup the HiZ bits. */
+        z->zb_bw_cntl |= R300_HIZ_ENABLE |
                 (r300->hiz_func == HIZ_FUNC_MIN ? R300_HIZ_MIN : R300_HIZ_MAX);
 
-            z->sc_hyperz |= R300_SC_HYPERZ_ENABLE |
-                            r300_get_sc_hz_max(r300);
+        z->sc_hyperz |= R300_SC_HYPERZ_ENABLE |
+                        r300_get_sc_hz_max(r300);
 
-            if (r300->screen->caps.is_r500) {
-                z->zb_bw_cntl |= R500_HIZ_EQUAL_REJECT_ENABLE;
-            }
+        if (r300->screen->caps.is_r500) {
+            z->zb_bw_cntl |= R500_HIZ_EQUAL_REJECT_ENABLE;
         }
     }
-
-    /* R500-specific features and optimizations. */
-    if (r300->screen->caps.is_r500) {
-        z->zb_bw_cntl |= R500_PEQ_PACKING_ENABLE |
-                         R500_COVERED_PTR_MASKING_ENABLE;
-    }
 }
 
 /*****************************************************************************/
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 24b41d5085d..bc6c67dd034 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -768,7 +768,6 @@ void r300_mark_fb_state_dirty(struct r300_context *r300,
                               enum r300_fb_state_change change)
 {
     struct pipe_framebuffer_state *state = r300->fb_state.state;
-    boolean can_hyperz = r300->rws->get_value(r300->rws, RADEON_VID_CAN_HYPERZ);
 
     r300_mark_atom_dirty(r300, &r300->gpu_flush);
     r300_mark_atom_dirty(r300, &r300->fb_state);
@@ -797,7 +796,7 @@ void r300_mark_fb_state_dirty(struct r300_context *r300,
         r300->fb_state.size += 10;
     else if (state->zsbuf) {
         r300->fb_state.size += 10;
-        if (can_hyperz)
+        if (r300->hyperz_enabled)
             r300->fb_state.size += 8;
     }
 
@@ -813,6 +812,7 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
     struct pipe_framebuffer_state *old_state = r300->fb_state.state;
     unsigned max_width, max_height, i;
     uint32_t zbuffer_bpp = 0;
+    boolean unlock_zbuffer = FALSE;
 
     if (r300->screen->caps.is_r500) {
         max_width = max_height = 4096;
@@ -828,7 +828,7 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
         return;
     }
 
-    if (old_state->zsbuf && r300->zmask_in_use && !r300->hyperz_locked) {
+    if (old_state->zsbuf && r300->zmask_in_use && !r300->locked_zbuffer) {
         /* There is a zmask in use, what are we gonna do? */
         if (state->zsbuf) {
             if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) {
@@ -838,10 +838,9 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
             }
         } else {
             /* We don't bind another zbuffer, so lock the current one. */
-            r300->hyperz_locked = TRUE;
             pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf);
         }
-    } else if (r300->hyperz_locked && r300->locked_zbuffer) {
+    } else if (r300->locked_zbuffer) {
         /* We have a locked zbuffer now, what are we gonna do? */
         if (state->zsbuf) {
             if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) {
@@ -851,11 +850,11 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
                 r300->hiz_in_use = FALSE;
             } else {
                 /* We are binding the locked zbuffer again, so unlock it. */
-                r300->hyperz_locked = FALSE;
+                unlock_zbuffer = TRUE;
             }
         }
     }
-    assert(state->zsbuf || r300->hyperz_locked || !r300->zmask_in_use);
+    assert(state->zsbuf || (r300->locked_zbuffer && !unlock_zbuffer) || !r300->zmask_in_use);
 
     /* Need to reset clamping or colormask. */
     r300_mark_atom_dirty(r300, &r300->blend_state);
@@ -870,7 +869,7 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
 
     util_copy_framebuffer_state(r300->fb_state.state, state);
 
-    if (!r300->hyperz_locked) {
+    if (unlock_zbuffer) {
         pipe_surface_reference(&r300->locked_zbuffer, NULL);
     }
 
diff --git a/src/gallium/drivers/r300/r300_state_derived.c b/src/gallium/drivers/r300/r300_state_derived.c
index afc1451183d..04499c78cc6 100644
--- a/src/gallium/drivers/r300/r300_state_derived.c
+++ b/src/gallium/drivers/r300/r300_state_derived.c
@@ -965,7 +965,7 @@ static void r300_decompress_depth_textures(struct r300_context *r300)
                           state->sampler_state_count);
     unsigned i;
 
-    if (!r300->hyperz_locked || !r300->locked_zbuffer) {
+    if (!r300->locked_zbuffer) {
         return;
     }
 
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 502f2663e8b..654b04ea1bd 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -310,6 +310,7 @@ static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 {
 	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 	union util_color uc;
+	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
 
 	if (rstate == NULL) {
 		return NULL;
@@ -321,9 +322,10 @@ static void *evergreen_create_sampler_state(struct pipe_context *ctx,
 			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
-			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
-			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+			S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
@@ -429,7 +431,9 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 				S_030014_LAST_LEVEL(state->u.tex.last_level) |
 				S_030014_BASE_ARRAY(0) |
 				S_030014_LAST_ARRAY(0), 0xffffffff, NULL);
-	r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL);
+	r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
+				S_030018_MAX_ANISO(4 /* max 16 samples */),
+				0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
 				S_03001C_DATA_FORMAT(format) |
 				S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 670606d9b07..3e878106bea 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1027,6 +1027,9 @@
 #define   G_030014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
 #define   C_030014_LAST_ARRAY                          0xC001FFFF
 #define R_030018_SQ_TEX_RESOURCE_WORD6_0             0x030018
+#define   S_030018_MAX_ANISO(x)                        (((x) & 0x7) << 0)
+#define   G_030018_MAX_ANISO(x)                        (((x) >> 0) & 0x7)
+#define   C_030018_MAX_ANISO                           0xFFFFFFF8
 #define   S_030018_PERF_MODULATION(x)                  (((x) & 0x7) << 3)
 #define   G_030018_PERF_MODULATION(x)                  (((x) >> 3) & 0x7)
 #define   C_030018_PERF_MODULATION                     0xFFFFFFC7
@@ -1141,6 +1144,9 @@
 #define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 15)
 #define   G_03C000_MIP_FILTER(x)                       (((x) >> 15) & 0x3)
 #define   C_03C000_MIP_FILTER                          0xFFFE7FFF
+#define   S_03C000_MAX_ANISO(x)                        (((x) & 0x7) << 17)
+#define   G_03C000_MAX_ANISO(x)                        (((x) >> 17) & 0x7)
+#define   C_03C000_MAX_ANISO                           0xFFF1FFFF
 #define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 20)
 #define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 20) & 0x3)
 #define   C_03C000_BORDER_COLOR_TYPE                   0xFFCFFFFF
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 33aa45088a8..7b57fc80dc2 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -193,8 +193,6 @@ struct r600_block {
 };
 
 struct r600_range {
-	unsigned		start_offset;
-	unsigned		end_offset;
 	struct r600_block	**blocks;
 };
 
@@ -239,9 +237,7 @@ struct r600_query {
 
 struct r600_context {
 	struct radeon		*radeon;
-	unsigned		hash_size;
-	unsigned		hash_shift;
-	struct r600_range	range[256];
+	struct r600_range	*range;
 	unsigned		nblocks;
 	struct r600_block	**blocks;
 	struct list_head	dirty;
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index aa5ef4efb3b..0e4cfeb5b80 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -317,4 +317,13 @@ static INLINE u32 S_FIXED(float value, u32 frac_bits)
 }
 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 
+static inline unsigned r600_tex_aniso_filter(unsigned filter)
+{
+	if (filter <= 1)   return 0;
+	if (filter <= 2)   return 1;
+	if (filter <= 4)   return 2;
+	if (filter <= 8)   return 3;
+	 /* else */        return 4;
+}
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b9084c953ee..8098e489d0f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -374,6 +374,7 @@ static void *r600_create_sampler_state(struct pipe_context *ctx,
 {
 	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 	union util_color uc;
+	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
 
 	if (rstate == NULL) {
 		return NULL;
@@ -385,9 +386,10 @@ static void *r600_create_sampler_state(struct pipe_context *ctx,
 			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
-			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
-			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+			S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
@@ -497,7 +499,8 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 				S_038014_BASE_ARRAY(state->u.tex.first_layer) |
 				S_038014_LAST_ARRAY(state->u.tex.last_layer), 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
-				S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL);
+				S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+				S_038018_MAX_ANISO(4 /* max 16 samples */), 0xFFFFFFFF, NULL);
 
 	return &resource->base;
 }
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 8296b52eb94..9281b08bd82 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -1012,6 +1012,9 @@
 #define   S_038018_MPEG_CLAMP(x)                       (((x) & 0x3) << 0)
 #define   G_038018_MPEG_CLAMP(x)                       (((x) >> 0) & 0x3)
 #define   C_038018_MPEG_CLAMP                          0xFFFFFFFC
+#define   S_038018_MAX_ANISO(x)                        (((x) & 0x7) << 2)
+#define   G_038018_MAX_ANISO(x)                        (((x) >> 2) & 0x7)
+#define   C_038018_MAX_ANISO                           0xFFFFFFE3
 #define   S_038018_PERF_MODULATION(x)                  (((x) & 0x7) << 5)
 #define   G_038018_PERF_MODULATION(x)                  (((x) >> 5) & 0x7)
 #define   C_038018_PERF_MODULATION                     0xFFFFFF1F
@@ -1090,6 +1093,9 @@
 #define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 17)
 #define   G_03C000_MIP_FILTER(x)                       (((x) >> 17) & 0x3)
 #define   C_03C000_MIP_FILTER                          0xFFF9FFFF
+#define   S_03C000_MAX_ANISO(x)                        (((x) & 0x7) << 19)
+#define   G_03C000_MAX_ANISO(x)                        (((x) >> 19) & 0x7)
+#define   C_03C000_MAX_ANISO                           0xFFB7FFFF
 #define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 22)
 #define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 22) & 0x3)
 #define   C_03C000_BORDER_COLOR_TYPE                   0xFF3FFFFF
@@ -1152,6 +1158,9 @@
 #define   S_03C008_PERF_Z(x)                           (((x) & 0x3) << 18)
 #define   G_03C008_PERF_Z(x)                           (((x) >> 18) & 0x3)
 #define   C_03C008_PERF_Z                              0xFFF3FFFF
+#define   S_03C008_ANISO_BIAS(x)                       (((x) & 0x3f) << 22)
+#define   G_03C008_ANISO_BIAS(x)                       (((x) >> 22) & 0x3f)
+#define   C_03C008_ANISO_BIAS                          (~(0x3f << 22))
 #define   S_03C008_FETCH_4(x)                          (((x) & 0x1) << 26)
 #define   G_03C008_FETCH_4(x)                          (((x) >> 26) & 0x1)
 #define   C_03C008_FETCH_4                             0xFBFFFFFF
diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c b/src/gallium/drivers/softpipe/sp_tex_sample.c
index 02892c16bde..1446aee2aa4 100644
--- a/src/gallium/drivers/softpipe/sp_tex_sample.c
+++ b/src/gallium/drivers/softpipe/sp_tex_sample.c
@@ -2243,8 +2243,8 @@ sp_sampler_variant_bind_view( struct sp_sampler_variant *samp,
 
    samp->view = view;
    samp->cache = tex_cache;
-   samp->xpot = util_unsigned_logbase2( texture->width0 );
-   samp->ypot = util_unsigned_logbase2( texture->height0 );
+   samp->xpot = util_logbase2( texture->width0 );
+   samp->ypot = util_logbase2( texture->height0 );
    samp->level = view->u.tex.first_level;
 }
 
diff --git a/src/gallium/include/pipe/p_config.h b/src/gallium/include/pipe/p_config.h
index 74a1fa29781..1818c8b9e9a 100644
--- a/src/gallium/include/pipe/p_config.h
+++ b/src/gallium/include/pipe/p_config.h
@@ -111,14 +111,28 @@
  * Endian detection.
  */
 
+#ifdef __GLIBC__
+#include <endian.h>
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+# define PIPE_ARCH_LITTLE_ENDIAN
+#elif __BYTE_ORDER == __BIG_ENDIAN
+# define PIPE_ARCH_BIG_ENDIAN
+#endif
+
+#else
+
 #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
 #define PIPE_ARCH_LITTLE_ENDIAN
 #elif defined(PIPE_ARCH_PPC) || defined(PIPE_ARCH_PPC_64)
 #define PIPE_ARCH_BIG_ENDIAN
-#else
-#define PIPE_ARCH_UNKNOWN_ENDIAN
 #endif
 
+#endif
+
+#if !defined(PIPE_ARCH_LITTLE_ENDIAN) && !defined(PIPE_ARCH_BIG_ENDIAN)
+#error Unknown Endianness
+#endif
 
 #if !defined(PIPE_OS_EMBEDDED)
 
diff --git a/src/gallium/state_trackers/egl/Makefile b/src/gallium/state_trackers/egl/Makefile
index 53673a78a94..763e7b58a49 100644
--- a/src/gallium/state_trackers/egl/Makefile
+++ b/src/gallium/state_trackers/egl/Makefile
@@ -6,6 +6,7 @@ common_INCLUDES = \
 	-I$(TOP)/src/gallium/include \
 	-I$(TOP)/src/gallium/auxiliary \
 	-I$(TOP)/src/egl/main \
+	-I$(TOP)/src/egl/wayland/wayland-drm/ \
 	-I$(TOP)/include
 
 common_SOURCES = $(wildcard common/*.c)
@@ -56,6 +57,7 @@ endif
 ifneq ($(findstring wayland, $(EGL_PLATFORMS)),)
 EGL_OBJECTS += $(wayland_OBJECTS)
 EGL_CPPFLAGS += -DHAVE_WAYLAND_BACKEND
+DEFINES += -DHAVE_WAYLAND_BACKEND
 endif
 ifneq ($(findstring drm, $(EGL_PLATFORMS)),)
 EGL_OBJECTS += $(drm_OBJECTS)
diff --git a/src/gallium/state_trackers/egl/common/egl_g3d.c b/src/gallium/state_trackers/egl/common/egl_g3d.c
index 2c7f3bde4f0..4bd865638a3 100644
--- a/src/gallium/state_trackers/egl/common/egl_g3d.c
+++ b/src/gallium/state_trackers/egl/common/egl_g3d.c
@@ -552,6 +552,11 @@ egl_g3d_initialize(_EGLDriver *drv, _EGLDisplay *dpy)
    if (dpy->Platform == _EGL_PLATFORM_WAYLAND && gdpy->native->buffer)
       dpy->Extensions.MESA_drm_image = EGL_TRUE;
 
+#ifdef EGL_WL_bind_wayland_display
+   if (gdpy->native->wayland_bufmgr)
+      dpy->Extensions.WL_bind_wayland_display = EGL_TRUE;
+#endif
+
    if (egl_g3d_add_configs(drv, dpy, 1) == 1) {
       _eglError(EGL_NOT_INITIALIZED, "eglInitialize(unable to add configs)");
       goto fail;
diff --git a/src/gallium/state_trackers/egl/common/egl_g3d_api.c b/src/gallium/state_trackers/egl/common/egl_g3d_api.c
index f1568329ecf..8b1821e0055 100644
--- a/src/gallium/state_trackers/egl/common/egl_g3d_api.c
+++ b/src/gallium/state_trackers/egl/common/egl_g3d_api.c
@@ -868,6 +868,34 @@ egl_g3d_show_screen_surface(_EGLDriver *drv, _EGLDisplay *dpy,
 
 #endif /* EGL_MESA_screen_surface */
 
+#ifdef EGL_WL_bind_wayland_display
+
+static EGLBoolean
+egl_g3d_bind_wayland_display_wl(_EGLDriver *drv, _EGLDisplay *dpy,
+                                struct wl_display *wl_dpy)
+{
+   struct egl_g3d_display *gdpy = egl_g3d_display(dpy);
+
+   if (!gdpy->native->wayland_bufmgr)
+      return EGL_FALSE;
+
+   return gdpy->native->wayland_bufmgr->bind_display(gdpy->native, wl_dpy);
+}
+
+static EGLBoolean
+egl_g3d_unbind_wayland_display_wl(_EGLDriver *drv, _EGLDisplay *dpy,
+                                  struct wl_display *wl_dpy)
+{
+   struct egl_g3d_display *gdpy = egl_g3d_display(dpy);
+
+   if (!gdpy->native->wayland_bufmgr)
+      return EGL_FALSE;
+
+   return gdpy->native->wayland_bufmgr->unbind_display(gdpy->native, wl_dpy);
+}
+
+#endif /* EGL_WL_bind_wayland_display */
+
 void
 egl_g3d_init_driver_api(_EGLDriver *drv)
 {
@@ -897,6 +925,11 @@ egl_g3d_init_driver_api(_EGLDriver *drv)
    drv->API.CreateDRMImageMESA = egl_g3d_create_drm_image;
    drv->API.ExportDRMImageMESA = egl_g3d_export_drm_image;
 #endif
+#ifdef EGL_WL_bind_wayland_display
+   drv->API.BindWaylandDisplayWL = egl_g3d_bind_wayland_display_wl;
+   drv->API.UnbindWaylandDisplayWL = egl_g3d_unbind_wayland_display_wl;
+
+#endif
 
 #ifdef EGL_KHR_reusable_sync
    drv->API.CreateSyncKHR = egl_g3d_create_sync;
diff --git a/src/gallium/state_trackers/egl/common/egl_g3d_image.c b/src/gallium/state_trackers/egl/common/egl_g3d_image.c
index e1c83168b3a..210b8c2ee82 100644
--- a/src/gallium/state_trackers/egl/common/egl_g3d_image.c
+++ b/src/gallium/state_trackers/egl/common/egl_g3d_image.c
@@ -179,6 +179,27 @@ egl_g3d_reference_drm_buffer(_EGLDisplay *dpy, EGLint name,
 
 #endif /* EGL_MESA_drm_image */
 
+#ifdef EGL_WL_bind_wayland_display
+
+static struct pipe_resource *
+egl_g3d_reference_wl_buffer(_EGLDisplay *dpy, struct wl_buffer *buffer,
+                            _EGLImage *img, const EGLint *attribs)
+{
+   struct egl_g3d_display *gdpy = egl_g3d_display(dpy);
+   struct pipe_resource *resource = NULL, *tmp = NULL;
+
+   if (!gdpy->native->wayland_bufmgr)
+      return NULL;
+
+   tmp = gdpy->native->wayland_bufmgr->buffer_get_resource(gdpy->native, buffer);
+
+   pipe_resource_reference(&resource, tmp);
+
+   return resource;
+}
+
+#endif /* EGL_WL_bind_wayland_display */
+
 _EGLImage *
 egl_g3d_create_image(_EGLDriver *drv, _EGLDisplay *dpy, _EGLContext *ctx,
                      EGLenum target, EGLClientBuffer buffer,
@@ -210,6 +231,12 @@ egl_g3d_create_image(_EGLDriver *drv, _EGLDisplay *dpy, _EGLContext *ctx,
             (EGLint) buffer, &gimg->base, attribs);
       break;
 #endif
+#ifdef EGL_WL_bind_wayland_display
+   case EGL_WAYLAND_BUFFER_WL:
+      ptex = egl_g3d_reference_wl_buffer(dpy,
+            (struct wl_buffer *) buffer, &gimg->base, attribs);
+      break;
+#endif
    default:
       ptex = NULL;
       break;
diff --git a/src/gallium/state_trackers/egl/common/native.h b/src/gallium/state_trackers/egl/common/native.h
index 9246f8c32a4..8646e52ed7c 100644
--- a/src/gallium/state_trackers/egl/common/native.h
+++ b/src/gallium/state_trackers/egl/common/native.h
@@ -40,6 +40,7 @@ extern "C" {
 
 #include "native_buffer.h"
 #include "native_modeset.h"
+#include "native_wayland_bufmgr.h"
 
 /**
  * Only color buffers are listed.  The others are allocated privately through,
@@ -198,6 +199,7 @@ struct native_display {
 
    const struct native_display_buffer *buffer;
    const struct native_display_modeset *modeset;
+   const struct native_display_wayland_bufmgr *wayland_bufmgr;
 };
 
 /**
diff --git a/src/gallium/state_trackers/egl/common/native_wayland_bufmgr.h b/src/gallium/state_trackers/egl/common/native_wayland_bufmgr.h
new file mode 100644
index 00000000000..b29fd15c1ae
--- /dev/null
+++ b/src/gallium/state_trackers/egl/common/native_wayland_bufmgr.h
@@ -0,0 +1,46 @@
+/*
+ * Mesa 3-D graphics library
+ * Version:  7.11
+ *
+ * Copyright (C) 2011 Benjamin Franzke <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NATIVE_WAYLAND_BUFMGR_H_
+#define _NATIVE_WAYLAND_BUFMGR_H_
+
+struct native_display;
+struct wl_display;
+struct wl_buffer;
+struct pipe_resource;
+
+struct native_display_wayland_bufmgr {
+   boolean (*bind_display)(struct native_display *ndpy,
+                           struct wl_display *wl_dpy);
+
+   boolean (*unbind_display)(struct native_display *ndpy,
+                             struct wl_display *wl_dpy);
+
+   struct pipe_resource *(*buffer_get_resource)(struct native_display *ndpy,
+                                                struct wl_buffer *buffer);
+                             
+};
+
+#endif /* _NATIVE_WAYLAND_BUFMGR_H_ */
diff --git a/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.c b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.c
new file mode 100644
index 00000000000..bc2cee4c386
--- /dev/null
+++ b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.c
@@ -0,0 +1,57 @@
+#include <stdint.h>
+#include <string.h>
+
+#include "native.h"
+#include "util/u_inlines.h"
+#include "state_tracker/drm_driver.h"
+
+#ifdef HAVE_WAYLAND_BACKEND
+
+#include <wayland-server.h>
+#include <wayland-drm-server-protocol.h>
+
+#include "native_wayland_drm_bufmgr_helper.h"
+
+void *
+egl_g3d_wl_drm_helper_reference_buffer(void *user_data, uint32_t name,
+                                       int32_t width, int32_t height,
+                                       uint32_t stride,
+                                       struct wl_visual *visual)
+{
+   struct native_display *ndpy = user_data;
+   struct pipe_resource templ;
+   struct winsys_handle wsh;
+   enum pipe_format format = PIPE_FORMAT_B8G8R8A8_UNORM;
+
+   memset(&templ, 0, sizeof(templ));
+   templ.target = PIPE_TEXTURE_2D;
+   templ.format = format;
+   templ.bind = PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW;
+   templ.width0 = width;
+   templ.height0 = height;
+   templ.depth0 = 1;
+   templ.array_size = 1;
+
+   memset(&wsh, 0, sizeof(wsh));
+   wsh.handle = name;
+   wsh.stride = stride;
+
+   return ndpy->screen->resource_from_handle(ndpy->screen, &templ, &wsh);
+}
+
+void
+egl_g3d_wl_drm_helper_unreference_buffer(void *user_data, void *buffer)
+{
+   struct pipe_resource *resource = buffer;
+
+   pipe_resource_reference(&resource, NULL);
+}
+
+struct pipe_resource *
+egl_g3d_wl_drm_common_wl_buffer_get_resource(struct native_display *ndpy,
+                                             struct wl_buffer *buffer)
+{
+   return wayland_drm_buffer_get_buffer(buffer);
+}
+
+#endif
diff --git a/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.h b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.h
new file mode 100644
index 00000000000..71cb6c52b26
--- /dev/null
+++ b/src/gallium/state_trackers/egl/common/native_wayland_drm_bufmgr_helper.h
@@ -0,0 +1,44 @@
+/*
+ * Mesa 3-D graphics library
+ * Version:  7.11
+ *
+ * Copyright (C) 2011 Benjamin Franzke <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _NATIVE_WAYLAND_DRM_BUFMGR_HELPER_H_
+#define _NATIVE_WAYLAND_DRM_BUFMGR_HELPER_H_
+
+#include "wayland-drm.h"
+
+void *
+egl_g3d_wl_drm_helper_reference_buffer(void *user_data, uint32_t name,
+                                       int32_t width, int32_t height,
+                                       uint32_t stride,
+                                       struct wl_visual *visual);
+
+void
+egl_g3d_wl_drm_helper_unreference_buffer(void *user_data, void *buffer);
+
+struct pipe_resource *
+egl_g3d_wl_drm_common_wl_buffer_get_resource(struct native_display *ndpy,
+                                             struct wl_buffer *buffer);
+
+#endif /* _NATIVE_WAYLAND_DRM_BUFMGR_HELPER_H_ */
diff --git a/src/gallium/state_trackers/egl/drm/native_drm.c b/src/gallium/state_trackers/egl/drm/native_drm.c
index 9863329ff40..c89a6d4767e 100644
--- a/src/gallium/state_trackers/egl/drm/native_drm.c
+++ b/src/gallium/state_trackers/egl/drm/native_drm.c
@@ -23,6 +23,7 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
+#include <string.h>
 #include <sys/types.h>
 #include <sys/stat.h>
 #include <fcntl.h>
@@ -36,6 +37,10 @@
 #include <radeon_drm.h>
 #include "radeon/drm/radeon_drm_public.h"
 
+#ifdef HAVE_LIBUDEV
+#include <libudev.h>
+#endif
+
 static boolean
 drm_display_is_format_supported(struct native_display *ndpy,
                                 enum pipe_format fmt, boolean is_color)
@@ -126,6 +131,9 @@ drm_display_destroy(struct native_display *ndpy)
 
    ndpy_uninit(ndpy);
 
+   if (drmdpy->device_name)
+      FREE(drmdpy->device_name);
+
    if (drmdpy->fd >= 0)
       close(drmdpy->fd);
 
@@ -207,6 +215,101 @@ static struct native_display_buffer drm_display_buffer = {
    drm_display_export_buffer
 };
 
+static int
+drm_display_authenticate(void *user_data, uint32_t magic)
+{
+   struct native_display *ndpy = user_data;
+   struct drm_display *drmdpy = drm_display(ndpy);
+
+   return drmAuthMagic(drmdpy->fd, magic);
+}
+
+static char *
+drm_get_device_name(int fd)
+{
+   char *device_name = NULL;
+#ifdef HAVE_LIBUDEV
+   struct udev *udev;
+   struct udev_device *device;
+   struct stat buf;
+   const char *tmp;
+
+   udev = udev_new();
+   if (fstat(fd, &buf) < 0) {
+      _eglLog(_EGL_WARNING, "failed to stat fd %d", fd);
+      goto out;
+   }
+
+   device = udev_device_new_from_devnum(udev, 'c', buf.st_rdev);
+   if (device == NULL) {
+      _eglLog(_EGL_WARNING,
+              "could not create udev device for fd %d", fd);
+      goto out;
+   }
+
+   tmp = udev_device_get_devnode(device);
+   if (!tmp)
+      goto out;
+   device_name = strdup(tmp);
+
+out:
+   udev_device_unref(device);
+   udev_unref(udev);
+
+#endif
+   return device_name;
+}
+
+#ifdef HAVE_WAYLAND_BACKEND
+
+static struct wayland_drm_callbacks wl_drm_callbacks = {
+   drm_display_authenticate,
+   egl_g3d_wl_drm_helper_reference_buffer,
+   egl_g3d_wl_drm_helper_unreference_buffer
+};
+
+static boolean
+drm_display_bind_wayland_display(struct native_display *ndpy,
+                                  struct wl_display *wl_dpy)
+{
+   struct drm_display *drmdpy = drm_display(ndpy);
+
+   if (drmdpy->wl_server_drm)
+      return FALSE;
+
+   drmdpy->wl_server_drm = wayland_drm_init(wl_dpy,
+         drmdpy->device_name,
+         &wl_drm_callbacks, ndpy);
+
+   if (!drmdpy->wl_server_drm)
+      return FALSE;
+   
+   return TRUE;
+}
+
+static boolean
+drm_display_unbind_wayland_display(struct native_display *ndpy,
+                                    struct wl_display *wl_dpy)
+{
+   struct drm_display *drmdpy = drm_display(ndpy);
+
+   if (!drmdpy->wl_server_drm)
+      return FALSE;
+
+   wayland_drm_uninit(drmdpy->wl_server_drm);
+   drmdpy->wl_server_drm = NULL;
+
+   return TRUE;
+}
+
+static struct native_display_wayland_bufmgr drm_display_wayland_bufmgr = {
+   drm_display_bind_wayland_display,
+   drm_display_unbind_wayland_display,
+   egl_g3d_wl_drm_common_wl_buffer_get_resource
+};
+
+#endif /* HAVE_WAYLAND_BACKEND */
+
 static struct native_display *
 drm_create_display(int fd, struct native_event_handler *event_handler,
                    void *user_data)
@@ -218,6 +321,7 @@ drm_create_display(int fd, struct native_event_handler *event_handler,
       return NULL;
 
    drmdpy->fd = fd;
+   drmdpy->device_name = drm_get_device_name(fd);
    drmdpy->event_handler = event_handler;
    drmdpy->base.user_data = user_data;
 
@@ -231,6 +335,10 @@ drm_create_display(int fd, struct native_event_handler *event_handler,
    drmdpy->base.get_configs = drm_display_get_configs;
 
    drmdpy->base.buffer = &drm_display_buffer;
+#ifdef HAVE_WAYLAND_BACKEND
+   if (drmdpy->device_name)
+      drmdpy->base.wayland_bufmgr = &drm_display_wayland_bufmgr;
+#endif
    drm_display_init_modeset(&drmdpy->base);
 
    return &drmdpy->base;
diff --git a/src/gallium/state_trackers/egl/drm/native_drm.h b/src/gallium/state_trackers/egl/drm/native_drm.h
index 7da9b45f23e..41cdc4f9d04 100644
--- a/src/gallium/state_trackers/egl/drm/native_drm.h
+++ b/src/gallium/state_trackers/egl/drm/native_drm.h
@@ -37,6 +37,10 @@
 #include "common/native.h"
 #include "common/native_helper.h"
 
+#ifdef HAVE_WAYLAND_BACKEND
+#include "common/native_wayland_drm_bufmgr_helper.h"
+#endif
+
 struct drm_config;
 struct drm_crtc;
 struct drm_connector;
@@ -49,6 +53,7 @@ struct drm_display {
    struct native_event_handler *event_handler;
 
    int fd;
+   char *device_name;
    struct drm_config *config;
 
    /* for modesetting */
@@ -59,6 +64,10 @@ struct drm_display {
    struct drm_surface **shown_surfaces;
    /* save the original settings of the CRTCs */
    struct drm_crtc *saved_crtcs;
+
+#ifdef HAVE_WAYLAND_BACKEND
+   struct wl_drm *wl_server_drm; /* for EGL_WL_bind_wayland_display */
+#endif
 };
 
 struct drm_config {
diff --git a/src/gallium/state_trackers/egl/wayland/native_drm.c b/src/gallium/state_trackers/egl/wayland/native_drm.c
index 604720f6e5f..f643c7cbbba 100644
--- a/src/gallium/state_trackers/egl/wayland/native_drm.c
+++ b/src/gallium/state_trackers/egl/wayland/native_drm.c
@@ -45,6 +45,8 @@
 #include "wayland-drm-client-protocol.h"
 #include "wayland-egl-priv.h"
 
+#include "common/native_wayland_drm_bufmgr_helper.h"
+
 #include <xf86drm.h>
 #include <sys/types.h>
 #include <sys/stat.h>
@@ -56,6 +58,7 @@ struct wayland_drm_display {
    struct native_event_handler *event_handler;
 
    struct wl_drm *wl_drm;
+   struct wl_drm *wl_server_drm; /* for EGL_WL_bind_wayland_display */
    int fd;
    char *device_name;
    boolean authenticated;
@@ -268,6 +271,71 @@ static struct native_display_buffer wayland_drm_display_buffer = {
    wayland_drm_display_export_buffer
 };
 
+static int
+wayland_drm_display_authenticate(void *user_data, uint32_t magic)
+{
+   struct native_display *ndpy = user_data;
+   struct wayland_drm_display *drmdpy = wayland_drm_display(ndpy);
+   boolean current_authenticate, authenticated;
+
+   current_authenticate = drmdpy->authenticated;
+
+   wl_drm_authenticate(drmdpy->wl_drm, magic);
+   force_roundtrip(drmdpy->base.dpy);
+   authenticated = drmdpy->authenticated;
+
+   drmdpy->authenticated = current_authenticate;
+
+   return authenticated ? 0 : -1;
+}
+
+static struct wayland_drm_callbacks wl_drm_callbacks = {
+   wayland_drm_display_authenticate,
+   egl_g3d_wl_drm_helper_reference_buffer,
+   egl_g3d_wl_drm_helper_unreference_buffer
+};
+
+static boolean
+wayland_drm_display_bind_wayland_display(struct native_display *ndpy,
+                                         struct wl_display *wl_dpy)
+{
+   struct wayland_drm_display *drmdpy = wayland_drm_display(ndpy);
+
+   if (drmdpy->wl_server_drm)
+      return FALSE;
+
+   drmdpy->wl_server_drm =
+      wayland_drm_init(wl_dpy, drmdpy->device_name,
+                       &wl_drm_callbacks, ndpy);
+
+   if (!drmdpy->wl_server_drm)
+      return FALSE;
+   
+   return TRUE;
+}
+
+static boolean
+wayland_drm_display_unbind_wayland_display(struct native_display *ndpy,
+                                           struct wl_display *wl_dpy)
+{
+   struct wayland_drm_display *drmdpy = wayland_drm_display(ndpy);
+
+   if (!drmdpy->wl_server_drm)
+      return FALSE;
+
+   wayland_drm_uninit(drmdpy->wl_server_drm);
+   drmdpy->wl_server_drm = NULL;
+
+   return TRUE;
+}
+
+static struct native_display_wayland_bufmgr wayland_drm_display_wayland_bufmgr = {
+   wayland_drm_display_bind_wayland_display,
+   wayland_drm_display_unbind_wayland_display,
+   egl_g3d_wl_drm_common_wl_buffer_get_resource
+};
+
+
 struct wayland_display *
 wayland_create_drm_display(struct wl_display *dpy,
                            struct native_event_handler *event_handler,
@@ -294,6 +362,7 @@ wayland_create_drm_display(struct wl_display *dpy,
    }
    drmdpy->base.base.destroy = wayland_drm_display_destroy;
    drmdpy->base.base.buffer = &wayland_drm_display_buffer;
+   drmdpy->base.base.wayland_bufmgr = &wayland_drm_display_wayland_bufmgr;
 
    drmdpy->base.create_buffer = wayland_create_drm_buffer;
 
diff --git a/src/gallium/state_trackers/egl/x11/native_dri2.c b/src/gallium/state_trackers/egl/x11/native_dri2.c
index 5afca67a4d4..a56d43428fc 100644
--- a/src/gallium/state_trackers/egl/x11/native_dri2.c
+++ b/src/gallium/state_trackers/egl/x11/native_dri2.c
@@ -38,6 +38,10 @@
 #include "native_x11.h"
 #include "x11_screen.h"
 
+#ifdef HAVE_WAYLAND_BACKEND
+#include "common/native_wayland_drm_bufmgr_helper.h"
+#endif
+
 #ifdef GLX_DIRECT_RENDERING
 
 struct dri2_display {
@@ -56,6 +60,9 @@ struct dri2_display {
    int num_configs;
 
    struct util_hash_table *surfaces;
+#ifdef HAVE_WAYLAND_BACKEND
+   struct wl_drm *wl_server_drm; /* for EGL_WL_bind_wayland_display */
+#endif
 };
 
 struct dri2_surface {
@@ -802,6 +809,65 @@ dri2_display_hash_table_compare(void *key1, void *key2)
    return ((char *) key1 - (char *) key2);
 }
 
+static int
+dri2_display_authenticate(void *user_data, uint32_t magic)
+{
+   struct native_display *ndpy = user_data;
+   struct dri2_display *dri2dpy = dri2_display(ndpy);
+
+   return x11_screen_authenticate(dri2dpy->xscr, magic);
+}
+
+#ifdef HAVE_WAYLAND_BACKEND
+
+static struct wayland_drm_callbacks wl_drm_callbacks = {
+   dri2_display_authenticate,
+   egl_g3d_wl_drm_helper_reference_buffer,
+   egl_g3d_wl_drm_helper_unreference_buffer
+};
+
+static boolean
+dri2_display_bind_wayland_display(struct native_display *ndpy,
+                                  struct wl_display *wl_dpy)
+{
+   struct dri2_display *dri2dpy = dri2_display(ndpy);
+
+   if (dri2dpy->wl_server_drm)
+      return FALSE;
+
+   dri2dpy->wl_server_drm = wayland_drm_init(wl_dpy,
+         x11_screen_get_device_name(dri2dpy->xscr),
+         &wl_drm_callbacks, ndpy);
+
+   if (!dri2dpy->wl_server_drm)
+      return FALSE;
+   
+   return TRUE;
+}
+
+static boolean
+dri2_display_unbind_wayland_display(struct native_display *ndpy,
+                                    struct wl_display *wl_dpy)
+{
+   struct dri2_display *dri2dpy = dri2_display(ndpy);
+
+   if (!dri2dpy->wl_server_drm)
+      return FALSE;
+
+   wayland_drm_uninit(dri2dpy->wl_server_drm);
+   dri2dpy->wl_server_drm = NULL;
+
+   return TRUE;
+}
+
+static struct native_display_wayland_bufmgr dri2_display_wayland_bufmgr = {
+   dri2_display_bind_wayland_display,
+   dri2_display_unbind_wayland_display,
+   egl_g3d_wl_drm_common_wl_buffer_get_resource
+};
+
+#endif /* HAVE_WAYLAND_BACKEND */
+
 struct native_display *
 x11_create_dri2_display(Display *dpy,
                         struct native_event_handler *event_handler,
@@ -851,6 +917,9 @@ x11_create_dri2_display(Display *dpy,
    dri2dpy->base.is_pixmap_supported = dri2_display_is_pixmap_supported;
    dri2dpy->base.create_window_surface = dri2_display_create_window_surface;
    dri2dpy->base.create_pixmap_surface = dri2_display_create_pixmap_surface;
+#ifdef HAVE_WAYLAND_BACKEND
+   dri2dpy->base.wayland_bufmgr = &dri2_display_wayland_bufmgr;
+#endif
 
    return &dri2dpy->base;
 }
diff --git a/src/gallium/state_trackers/egl/x11/x11_screen.c b/src/gallium/state_trackers/egl/x11/x11_screen.c
index c919b79eac8..f1cc4400ba5 100644
--- a/src/gallium/state_trackers/egl/x11/x11_screen.c
+++ b/src/gallium/state_trackers/egl/x11/x11_screen.c
@@ -307,6 +307,23 @@ x11_screen_enable_dri2(struct x11_screen *xscr,
    return xscr->dri_fd;
 }
 
+char *
+x11_screen_get_device_name(struct x11_screen *xscr)
+{
+   return xscr->dri_device;
+}
+
+int
+x11_screen_authenticate(struct x11_screen *xscr, uint32_t id)
+{
+   boolean authenticated;
+
+   authenticated = DRI2Authenticate(xscr->dpy,
+         RootWindow(xscr->dpy, xscr->number), id);
+   
+   return authenticated ? 0 : -1;
+}
+
 /**
  * Create/Destroy the DRI drawable.
  */
diff --git a/src/gallium/state_trackers/egl/x11/x11_screen.h b/src/gallium/state_trackers/egl/x11/x11_screen.h
index 2e313e0148e..acf1300e9d1 100644
--- a/src/gallium/state_trackers/egl/x11/x11_screen.h
+++ b/src/gallium/state_trackers/egl/x11/x11_screen.h
@@ -97,6 +97,12 @@ x11_screen_enable_dri2(struct x11_screen *xscr,
                        x11_drawable_invalidate_buffers invalidate_buffers,
                        void *user_data);
 
+char *
+x11_screen_get_device_name(struct x11_screen *xscr);
+
+int
+x11_screen_authenticate(struct x11_screen *xscr, uint32_t id);
+
 void
 x11_drawable_enable_dri2(struct x11_screen *xscr,
                          Drawable drawable, boolean on);
diff --git a/src/gallium/state_trackers/wgl/stw_framebuffer.c b/src/gallium/state_trackers/wgl/stw_framebuffer.c
index 4033365bfbe..7a689f9977d 100644
--- a/src/gallium/state_trackers/wgl/stw_framebuffer.c
+++ b/src/gallium/state_trackers/wgl/stw_framebuffer.c
@@ -146,8 +146,6 @@ stw_framebuffer_get_size( struct stw_framebuffer *fb )
        * maximized again.
        */
 
-      assert(width == 0 && height == 0);
-
       return;
    }
 
diff --git a/src/gallium/state_trackers/xorg/xorg_exa.c b/src/gallium/state_trackers/xorg/xorg_exa.c
index 91c206f1872..b072f53aa91 100644
--- a/src/gallium/state_trackers/xorg/xorg_exa.c
+++ b/src/gallium/state_trackers/xorg/xorg_exa.c
@@ -49,9 +49,24 @@
 #include "util/u_box.h"
 #include "util/u_surface.h"
 
-#define DEBUG_PRINT 0
 #define ROUND_UP_TEXTURES 1
 
+static INLINE void
+exa_debug_printf(const char *format, ...) _util_printf_format(1,2);
+
+static INLINE void
+exa_debug_printf(const char *format, ...)
+{
+#if 0
+   va_list ap;
+   va_start(ap, format);
+   _debug_vprintf(format, ap);
+   va_end(ap);
+#else
+   (void) format; /* silence warning */
+#endif
+}
+
 /*
  * Helper functions
  */
@@ -195,10 +210,8 @@ ExaDownloadFromScreen(PixmapPtr pPix, int x,  int y, int w,  int h, char *dst,
     if (!transfer)
 	return FALSE;
 
-#if DEBUG_PRINT
-    debug_printf("------ ExaDownloadFromScreen(%d, %d, %d, %d, %d)\n",
+    exa_debug_printf("------ ExaDownloadFromScreen(%d, %d, %d, %d, %d)\n",
                  x, y, w, h, dst_pitch);
-#endif
 
     util_copy_rect((unsigned char*)dst, priv->tex->format, dst_pitch, 0, 0,
 		   w, h, exa->pipe->transfer_map(exa->pipe, transfer),
@@ -229,10 +242,8 @@ ExaUploadToScreen(PixmapPtr pPix, int x, int y, int w, int h, char *src,
     if (!transfer)
 	return FALSE;
 
-#if DEBUG_PRINT
-    debug_printf("++++++ ExaUploadToScreen(%d, %d, %d, %d, %d)\n",
+    exa_debug_printf("++++++ ExaUploadToScreen(%d, %d, %d, %d, %d)\n",
                  x, y, w, h, src_pitch);
-#endif
 
     util_copy_rect(exa->pipe->transfer_map(exa->pipe, transfer),
 		   priv->tex->format, transfer->stride, 0, 0, w, h,
@@ -261,6 +272,8 @@ ExaPrepareAccess(PixmapPtr pPix, int index)
     if (!priv->tex)
 	return FALSE;
 
+    exa_debug_printf("ExaPrepareAccess %d\n", index);
+
     if (priv->map_count == 0)
     {
         assert(pPix->drawable.width <= priv->tex->width0);
@@ -289,6 +302,8 @@ ExaPrepareAccess(PixmapPtr pPix, int index)
 
     priv->map_count++;
 
+    exa_debug_printf("ExaPrepareAccess %d prepared\n", index);
+
     return TRUE;
 }
 
@@ -308,6 +323,8 @@ ExaFinishAccess(PixmapPtr pPix, int index)
     if (!priv->map_transfer)
 	return;
 
+    exa_debug_printf("ExaFinishAccess %d\n", index);
+
     if (--priv->map_count == 0) {
 	assert(priv->map_transfer);
 	exa->pipe->transfer_unmap(exa->pipe, priv->map_transfer);
@@ -315,6 +332,8 @@ ExaFinishAccess(PixmapPtr pPix, int index)
 	priv->map_transfer = NULL;
 	pPix->devPrivate.ptr = NULL;
     }
+
+    exa_debug_printf("ExaFinishAccess %d finished\n", index);
 }
 
 /***********************************************************************
@@ -329,9 +348,8 @@ ExaPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planeMask, Pixel fg)
     struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pPixmap);
     struct exa_context *exa = ms->exa;
 
-#if DEBUG_PRINT
-    debug_printf("ExaPrepareSolid(0x%x)\n", fg);
-#endif
+    exa_debug_printf("ExaPrepareSolid(0x%x)\n", fg);
+
     if (!exa->accel)
 	return FALSE;
 
@@ -364,9 +382,7 @@ ExaSolid(PixmapPtr pPixmap, int x0, int y0, int x1, int y1)
     struct exa_context *exa = ms->exa;
     struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pPixmap);
 
-#if DEBUG_PRINT
-    debug_printf("\tExaSolid(%d, %d, %d, %d)\n", x0, y0, x1, y1);
-#endif
+    exa_debug_printf("\tExaSolid(%d, %d, %d, %d)\n", x0, y0, x1, y1);
 
     if (x0 == 0 && y0 == 0 &&
         x1 == pPixmap->drawable.width && y1 == pPixmap->drawable.height) {
@@ -388,8 +404,10 @@ ExaDoneSolid(PixmapPtr pPixmap)
 
     if (!priv)
 	return;
-   
+
+    exa_debug_printf("ExaDoneSolid\n");
     xorg_composite_done(exa);
+    exa_debug_printf("ExaDoneSolid done\n");
 }
 
 /***********************************************************************
@@ -406,9 +424,7 @@ ExaPrepareCopy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir,
     struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pDstPixmap);
     struct exa_pixmap_priv *src_priv = exaGetPixmapDriverPrivate(pSrcPixmap);
 
-#if DEBUG_PRINT
-    debug_printf("ExaPrepareCopy\n");
-#endif
+    exa_debug_printf("ExaPrepareCopy\n");
 
     if (!exa->accel)
 	return FALSE;
@@ -488,10 +504,8 @@ ExaCopy(PixmapPtr pDstPixmap, int srcX, int srcY, int dstX, int dstY,
    struct exa_context *exa = ms->exa;
    struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pDstPixmap);
 
-#if DEBUG_PRINT
-   debug_printf("\tExaCopy(srcx=%d, srcy=%d, dstX=%d, dstY=%d, w=%d, h=%d)\n",
+   exa_debug_printf("\tExaCopy(srcx=%d, srcy=%d, dstX=%d, dstY=%d, w=%d, h=%d)\n",
                 srcX, srcY, dstX, dstY, width, height);
-#endif
 
    debug_assert(priv == exa->copy.dst);
    (void) priv;
@@ -527,12 +541,16 @@ ExaDoneCopy(PixmapPtr pPixmap)
     if (!priv)
 	return;
 
+   exa_debug_printf("ExaDoneCopy\n");
+
    renderer_draw_flush(exa->renderer);
 
    exa->copy.src = NULL;
    exa->copy.dst = NULL;
    pipe_surface_reference(&exa->copy.dst_surface, NULL);
    pipe_resource_reference(&exa->copy.src_texture, NULL);
+
+   exa_debug_printf("ExaDoneCopy done\n");
 }
 
 
@@ -584,19 +602,15 @@ ExaCheckComposite(int op,
    ScrnInfoPtr pScrn = xf86Screens[pDstPicture->pDrawable->pScreen->myNum];
    modesettingPtr ms = modesettingPTR(pScrn);
    struct exa_context *exa = ms->exa;
-
-#if DEBUG_PRINT
-   debug_printf("ExaCheckComposite(%d, %p, %p, %p) = %d\n",
-                op, pSrcPicture, pMaskPicture, pDstPicture, accelerated);
-#endif
-
-   if (!exa->accel)
-       return FALSE;
-
-   return xorg_composite_accelerated(op,
+   Bool accelerated = exa->accel && xorg_composite_accelerated(op,
 				     pSrcPicture,
 				     pMaskPicture,
 				     pDstPicture);
+
+   exa_debug_printf("ExaCheckComposite(%d, %p, %p, %p) = %d\n",
+                op, pSrcPicture, pMaskPicture, pDstPicture, accelerated);
+
+   return accelerated;
 }
 
 
@@ -613,14 +627,13 @@ ExaPrepareComposite(int op, PicturePtr pSrcPicture,
    if (!exa->accel)
        return FALSE;
 
-#if DEBUG_PRINT
-   debug_printf("ExaPrepareComposite(%d, src=0x%p, mask=0x%p, dst=0x%p)\n",
+   exa_debug_printf("ExaPrepareComposite(%d, src=0x%p, mask=0x%p, dst=0x%p)\n",
                 op, pSrcPicture, pMaskPicture, pDstPicture);
-   debug_printf("\tFormats: src(%s), mask(%s), dst(%s)\n",
+   exa_debug_printf("\tFormats: src(%s), mask(%s), dst(%s)\n",
                 pSrcPicture ? render_format_name(pSrcPicture->format) : "none",
                 pMaskPicture ? render_format_name(pMaskPicture->format) : "none",
                 pDstPicture ? render_format_name(pDstPicture->format) : "none");
-#endif
+
    if (!exa->pipe)
       XORG_FALLBACK("accel not enabled");
 
@@ -687,12 +700,10 @@ ExaComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
    struct exa_context *exa = ms->exa;
    struct exa_pixmap_priv *priv = exaGetPixmapDriverPrivate(pDst);
 
-#if DEBUG_PRINT
-   debug_printf("\tExaComposite(src[%d,%d], mask=[%d, %d], dst=[%d, %d], dim=[%d, %d])\n",
+   exa_debug_printf("\tExaComposite(src[%d,%d], mask=[%d, %d], dst=[%d, %d], dim=[%d, %d])\n",
                 srcX, srcY, maskX, maskY, dstX, dstY, width, height);
-   debug_printf("\t   Num bound samplers = %d\n",
+   exa_debug_printf("\t   Num bound samplers = %d\n",
                 exa->num_bound_samplers);
-#endif
 
    xorg_composite(exa, priv, srcX, srcY, maskX, maskY,
                   dstX, dstY, width, height);
diff --git a/src/gallium/targets/egl/Makefile b/src/gallium/targets/egl/Makefile
index 9d76a706122..a455b61af98 100644
--- a/src/gallium/targets/egl/Makefile
+++ b/src/gallium/targets/egl/Makefile
@@ -49,6 +49,7 @@ endif
 ifneq ($(findstring wayland, $(EGL_PLATFORMS)),)
 egl_SYS += $(WAYLAND_LIBS) $(LIBDRM_LIB)
 egl_LIBS += $(TOP)/src/gallium/winsys/sw/wayland/libws_wayland.a
+egl_LIBS += $(TOP)/src/egl/wayland/wayland-drm/libwayland-drm.a
 endif
 ifneq ($(findstring drm, $(EGL_PLATFORMS)),)
 egl_SYS += $(LIBDRM_LIB)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 0a5b1a09336..2a2c37ff606 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -41,432 +41,432 @@
 #define GROUP_FORCE_NEW_BLOCK	0
 
 static const struct r600_reg evergreen_config_reg_list[] = {
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008A14_PA_CL_ENHANCE, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_009100_SPI_CONFIG_CNTL, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET, R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0},
+	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
+	{R_008A14_PA_CL_ENHANCE, 0, 0, 0},
+	{R_008C00_SQ_CONFIG, 0, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
+	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
+	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
+	{R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 0, 0, 0},
+	{R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, 0, 0, 0},
+	{R_008C20_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
+	{R_008C24_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
+	{R_008C28_SQ_STACK_RESOURCE_MGMT_3, 0, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
+	{R_009100_SPI_CONFIG_CNTL, 0, 0, 0},
+	{R_00913C_SPI_CONFIG_CNTL_1, 0, 0, 0},
 };
 
 static const struct r600_reg evergreen_ctl_const_list[] = {
-	{PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
-	{PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
+	{R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
+	{R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
 };
 
 static const struct r600_reg evergreen_context_reg_list[] = {
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028000_DB_RENDER_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028004_DB_COUNT_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028008_DB_DEPTH_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028044_DB_STENCIL_INFO, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028058_DB_DEPTH_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02805C_DB_DEPTH_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285BC_PA_CL_UCP0_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C0_PA_CL_UCP0_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C4_PA_CL_UCP0_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285C8_PA_CL_UCP0_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285CC_PA_CL_UCP1_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D0_PA_CL_UCP1_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D4_PA_CL_UCP1_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285D8_PA_CL_UCP1_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285DC_PA_CL_UCP2_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E0_PA_CL_UCP2_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E4_PA_CL_UCP2_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285E8_PA_CL_UCP2_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285EC_PA_CL_UCP3_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F0_PA_CL_UCP3_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F4_PA_CL_UCP3_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285F8_PA_CL_UCP3_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0285FC_PA_CL_UCP4_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028600_PA_CL_UCP4_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028604_PA_CL_UCP4_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028608_PA_CL_UCP4_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02860C_PA_CL_UCP5_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028610_PA_CL_UCP5_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028614_PA_CL_UCP5_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028618_PA_CL_UCP5_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_3, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_5, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_6, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_7, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028640_SPI_VS_OUT_ID_9, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E0_SPI_BARYC_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028ABC_DB_HTILE_SURFACE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C3C_PA_SC_AA_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C64_CB_COLOR0_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C68_CB_COLOR0_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C6C_CB_COLOR0_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C78_CB_COLOR0_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA0_CB_COLOR1_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA4_CB_COLOR1_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CA8_CB_COLOR1_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CB4_CB_COLOR1_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CDC_CB_COLOR2_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE0_CB_COLOR2_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE4_CB_COLOR2_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028CF0_CB_COLOR2_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D18_CB_COLOR3_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D1C_CB_COLOR3_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D20_CB_COLOR3_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D2C_CB_COLOR3_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D54_CB_COLOR4_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D58_CB_COLOR4_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D5C_CB_COLOR4_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D68_CB_COLOR4_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D90_CB_COLOR5_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D94_CB_COLOR5_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D98_CB_COLOR5_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DA4_CB_COLOR5_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DCC_CB_COLOR6_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD0_CB_COLOR6_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD4_CB_COLOR6_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028DE0_CB_COLOR6_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E08_CB_COLOR7_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E0C_CB_COLOR7_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E10_CB_COLOR7_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E1C_CB_COLOR7_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E44_CB_COLOR8_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E48_CB_COLOR8_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E4C_CB_COLOR8_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E58_CB_COLOR8_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E60_CB_COLOR9_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E64_CB_COLOR9_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E68_CB_COLOR9_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E74_CB_COLOR9_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E7C_CB_COLOR10_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E80_CB_COLOR10_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E84_CB_COLOR10_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E90_CB_COLOR10_DIM, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E98_CB_COLOR11_PITCH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028E9C_CB_COLOR11_SLICE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA0_CB_COLOR11_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET, R_028EAC_CB_COLOR11_DIM, 0, 0, 0},
+	{R_028000_DB_RENDER_CONTROL, 0, 0, 0},
+	{R_028004_DB_COUNT_CONTROL, 0, 0, 0},
+	{R_028008_DB_DEPTH_VIEW, 0, 0, 0},
+	{R_02800C_DB_RENDER_OVERRIDE, 0, 0, 0},
+	{R_028010_DB_RENDER_OVERRIDE2, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028014_DB_HTILE_DATA_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
+	{R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
+	{R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
+	{R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028040_DB_Z_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028044_DB_STENCIL_INFO, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028048_DB_Z_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_02804C_DB_STENCIL_READ_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028050_DB_Z_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028054_DB_STENCIL_WRITE_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028058_DB_DEPTH_SIZE, 0, 0, 0},
+	{R_02805C_DB_DEPTH_SLICE, 0, 0, 0},
+	{R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
+	{R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
+	{R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
+	{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
+	{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
+	{R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
+	{R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
+	{R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
+	{R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
+	{R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
+	{R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
+	{R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
+	{R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
+	{R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
+	{R_028230_PA_SC_EDGERULE, 0, 0, 0},
+	{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0, 0},
+	{R_028238_CB_TARGET_MASK, 0, 0, 0},
+	{R_02823C_CB_SHADER_MASK, 0, 0, 0},
+	{R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
+	{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
+	{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
+	{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
+	{R_028350_SX_MISC, 0, 0, 0},
+	{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
+	{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
+	{R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
+	{R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
+	{R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
+	{R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
+	{R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
+	{R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
+	{R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
+	{R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
+	{R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
+	{R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
+	{R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
+	{R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
+	{R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
+	{R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
+	{R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
+	{R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
+	{R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
+	{R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
+	{R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
+	{R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
+	{R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
+	{R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
+	{R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
+	{R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
+	{R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
+	{R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
+	{R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
+	{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
+	{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
+	{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
+	{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
+	{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
+	{R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
+	{R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
+	{R_028408_VGT_INDX_OFFSET, 0, 0, 0},
+	{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
+	{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
+	{R_028414_CB_BLEND_RED, 0, 0, 0},
+	{R_028418_CB_BLEND_GREEN, 0, 0, 0},
+	{R_02841C_CB_BLEND_BLUE, 0, 0, 0},
+	{R_028420_CB_BLEND_ALPHA, 0, 0, 0},
+	{R_028430_DB_STENCILREFMASK, 0, 0, 0},
+	{R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
+	{R_028438_SX_ALPHA_REF, 0, 0, 0},
+	{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
+	{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
+	{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
+	{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
+	{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
+	{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
+	{R_0285BC_PA_CL_UCP0_X, 0, 0, 0},
+	{R_0285C0_PA_CL_UCP0_Y, 0, 0, 0},
+	{R_0285C4_PA_CL_UCP0_Z, 0, 0, 0},
+	{R_0285C8_PA_CL_UCP0_W, 0, 0, 0},
+	{R_0285CC_PA_CL_UCP1_X, 0, 0, 0},
+	{R_0285D0_PA_CL_UCP1_Y, 0, 0, 0},
+	{R_0285D4_PA_CL_UCP1_Z, 0, 0, 0},
+	{R_0285D8_PA_CL_UCP1_W, 0, 0, 0},
+	{R_0285DC_PA_CL_UCP2_X, 0, 0, 0},
+	{R_0285E0_PA_CL_UCP2_Y, 0, 0, 0},
+	{R_0285E4_PA_CL_UCP2_Z, 0, 0, 0},
+	{R_0285E8_PA_CL_UCP2_W, 0, 0, 0},
+	{R_0285EC_PA_CL_UCP3_X, 0, 0, 0},
+	{R_0285F0_PA_CL_UCP3_Y, 0, 0, 0},
+	{R_0285F4_PA_CL_UCP3_Z, 0, 0, 0},
+	{R_0285F8_PA_CL_UCP3_W, 0, 0, 0},
+	{R_0285FC_PA_CL_UCP4_X, 0, 0, 0},
+	{R_028600_PA_CL_UCP4_Y, 0, 0, 0},
+	{R_028604_PA_CL_UCP4_Z, 0, 0, 0},
+	{R_028608_PA_CL_UCP4_W, 0, 0, 0},
+	{R_02860C_PA_CL_UCP5_X, 0, 0, 0},
+	{R_028610_PA_CL_UCP5_Y, 0, 0, 0},
+	{R_028614_PA_CL_UCP5_Z, 0, 0, 0},
+	{R_028618_PA_CL_UCP5_W, 0, 0, 0},
+	{R_02861C_SPI_VS_OUT_ID_0, 0, 0, 0},
+	{R_028620_SPI_VS_OUT_ID_1, 0, 0, 0},
+	{R_028624_SPI_VS_OUT_ID_2, 0, 0, 0},
+	{R_028628_SPI_VS_OUT_ID_3, 0, 0, 0},
+	{R_02862C_SPI_VS_OUT_ID_4, 0, 0, 0},
+	{R_028630_SPI_VS_OUT_ID_5, 0, 0, 0},
+	{R_028634_SPI_VS_OUT_ID_6, 0, 0, 0},
+	{R_028638_SPI_VS_OUT_ID_7, 0, 0, 0},
+	{R_02863C_SPI_VS_OUT_ID_8, 0, 0, 0},
+	{R_028640_SPI_VS_OUT_ID_9, 0, 0, 0},
+	{R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
+	{R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
+	{R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
+	{R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
+	{R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
+	{R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
+	{R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
+	{R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
+	{R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
+	{R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
+	{R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
+	{R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
+	{R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
+	{R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
+	{R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
+	{R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
+	{R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
+	{R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
+	{R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
+	{R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
+	{R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
+	{R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
+	{R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
+	{R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
+	{R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
+	{R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
+	{R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
+	{R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
+	{R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
+	{R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
+	{R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
+	{R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
+	{R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
+	{R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
+	{R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
+	{R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
+	{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
+	{R_0286D8_SPI_INPUT_Z, 0, 0, 0},
+	{R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
+	{R_0286E0_SPI_BARYC_CNTL, 0, 0, 0},
+	{R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0, 0},
+	{R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0, 0},
+	{R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
+	{R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
+	{R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
+	{R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
+	{R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
+	{R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
+	{R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
+	{R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
+	{R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
+	{R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
+	{R_028808_CB_COLOR_CONTROL, 0, 0, 0},
+	{R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
+	{R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
+	{R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
+	{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
+	{R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
+	{R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0, 0},
+	{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028844_SQ_PGM_RESOURCES_PS, 0, 0, 0},
+	{R_028848_SQ_PGM_RESOURCES_2_PS, 0, 0, 0},
+	{R_02884C_SQ_PGM_EXPORTS_PS, 0, 0, 0},
+	{R_02885C_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028860_SQ_PGM_RESOURCES_VS, 0, 0, 0},
+	{R_028864_SQ_PGM_RESOURCES_2_VS, 0, 0, 0},
+	{R_0288A4_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_0288A8_SQ_PGM_RESOURCES_FS, 0, 0, 0},
+	{R_0288EC_SQ_LDS_ALLOC_PS, 0, 0, 0},
+	{R_028900_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
+	{R_028904_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
+	{R_028908_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_028910_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_028914_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_02891C_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
+	{R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0, 0},
+	{R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0, 0},
+	{R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0, 0},
+	{R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
+	{R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
+	{R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
+	{R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
+	{R_028A14_VGT_HOS_CNTL, 0, 0, 0},
+	{R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
+	{R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
+	{R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
+	{R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
+	{R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
+	{R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
+	{R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
+	{R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
+	{R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
+	{R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
+	{R_028A40_VGT_GS_MODE, 0, 0, 0},
+	{R_028A48_PA_SC_MODE_CNTL_0, 0, 0, 0},
+	{R_028A4C_PA_SC_MODE_CNTL_1, 0, 0, 0},
+	{R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
+	{R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
+	{R_028ABC_DB_HTILE_SURFACE, 0, 0, 0},
+	{R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0, 0, 0},
+	{R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
+	{R_028AC8_DB_PRELOAD_CONTROL, 0, 0, 0},
+	{R_028B54_VGT_SHADER_STAGES_EN, 0, 0, 0},
+	{R_028B70_DB_ALPHA_TO_MASK, 0, 0, 0},
+	{R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
+	{R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
+	{R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
+	{R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
+	{R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
+	{R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
+	{R_028B94_VGT_STRMOUT_CONFIG, 0, 0, 0},
+	{R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0, 0, 0},
+	{R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
+	{R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
+	{R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
+	{R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
+	{R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
+	{R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
+	{R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
+	{R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
+	{R_028C3C_PA_SC_AA_MASK, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028C60_CB_COLOR0_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028C64_CB_COLOR0_PITCH, 0, 0, 0},
+	{R_028C68_CB_COLOR0_SLICE, 0, 0, 0},
+	{R_028C6C_CB_COLOR0_VIEW, 0, 0, 0},
+	{R_028C70_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028C74_CB_COLOR0_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028C78_CB_COLOR0_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028C9C_CB_COLOR1_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CA0_CB_COLOR1_PITCH, 0, 0, 0},
+	{R_028CA4_CB_COLOR1_SLICE, 0, 0, 0},
+	{R_028CA8_CB_COLOR1_VIEW, 0, 0, 0},
+	{R_028CAC_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028CB0_CB_COLOR1_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CB4_CB_COLOR1_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028CD8_CB_COLOR2_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CDC_CB_COLOR2_PITCH, 0, 0, 0},
+	{R_028CE0_CB_COLOR2_SLICE, 0, 0, 0},
+	{R_028CE4_CB_COLOR2_VIEW, 0, 0, 0},
+	{R_028CE8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028CEC_CB_COLOR2_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028CF0_CB_COLOR2_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028D14_CB_COLOR3_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D18_CB_COLOR3_PITCH, 0, 0, 0},
+	{R_028D1C_CB_COLOR3_SLICE, 0, 0, 0},
+	{R_028D20_CB_COLOR3_VIEW, 0, 0, 0},
+	{R_028D24_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028D28_CB_COLOR3_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D2C_CB_COLOR3_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028D50_CB_COLOR4_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D54_CB_COLOR4_PITCH, 0, 0, 0},
+	{R_028D58_CB_COLOR4_SLICE, 0, 0, 0},
+	{R_028D5C_CB_COLOR4_VIEW, 0, 0, 0},
+	{R_028D60_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028D64_CB_COLOR4_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D68_CB_COLOR4_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028D8C_CB_COLOR5_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D90_CB_COLOR5_PITCH, 0, 0, 0},
+	{R_028D94_CB_COLOR5_SLICE, 0, 0, 0},
+	{R_028D98_CB_COLOR5_VIEW, 0, 0, 0},
+	{R_028D9C_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028DA0_CB_COLOR5_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028DA4_CB_COLOR5_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028DC8_CB_COLOR6_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028DCC_CB_COLOR6_PITCH, 0, 0, 0},
+	{R_028DD0_CB_COLOR6_SLICE, 0, 0, 0},
+	{R_028DD4_CB_COLOR6_VIEW, 0, 0, 0},
+	{R_028DD8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028DDC_CB_COLOR6_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028DE0_CB_COLOR6_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E04_CB_COLOR7_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E08_CB_COLOR7_PITCH, 0, 0, 0},
+	{R_028E0C_CB_COLOR7_SLICE, 0, 0, 0},
+	{R_028E10_CB_COLOR7_VIEW, 0, 0, 0},
+	{R_028E14_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E18_CB_COLOR7_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E1C_CB_COLOR7_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E40_CB_COLOR8_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E44_CB_COLOR8_PITCH, 0, 0, 0},
+	{R_028E48_CB_COLOR8_SLICE, 0, 0, 0},
+	{R_028E4C_CB_COLOR8_VIEW, 0, 0, 0},
+	{R_028E50_CB_COLOR8_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E54_CB_COLOR8_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E58_CB_COLOR8_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E5C_CB_COLOR9_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E60_CB_COLOR9_PITCH, 0, 0, 0},
+	{R_028E64_CB_COLOR9_SLICE, 0, 0, 0},
+	{R_028E68_CB_COLOR9_VIEW, 0, 0, 0},
+	{R_028E6C_CB_COLOR9_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E70_CB_COLOR9_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E74_CB_COLOR9_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E78_CB_COLOR10_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E7C_CB_COLOR10_PITCH, 0, 0, 0},
+	{R_028E80_CB_COLOR10_SLICE, 0, 0, 0},
+	{R_028E84_CB_COLOR10_VIEW, 0, 0, 0},
+	{R_028E88_CB_COLOR10_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028E8C_CB_COLOR10_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E90_CB_COLOR10_DIM, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028E94_CB_COLOR11_BASE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028E98_CB_COLOR11_PITCH, 0, 0, 0},
+	{R_028E9C_CB_COLOR11_SLICE, 0, 0, 0},
+	{R_028EA0_CB_COLOR11_VIEW, 0, 0, 0},
+	{R_028EA4_CB_COLOR11_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028EA8_CB_COLOR11_ATTRIB, REG_FLAG_NEED_BO, 0, 0},
+	{R_028EAC_CB_COLOR11_DIM, 0, 0, 0},
 };
 
 /* SHADER RESOURCE R600/R700 */
 static int evergreen_state_resource_init(struct r600_context *ctx, u32 offset)
 {
 	struct r600_reg r600_shader_resource[] = {
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030000_RESOURCE0_WORD0, 0, 0, 0},
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030004_RESOURCE0_WORD1, 0, 0, 0},
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03000C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030010_RESOURCE0_WORD4, 0, 0, 0},
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030014_RESOURCE0_WORD5, 0, 0, 0},
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_030018_RESOURCE0_WORD6, 0, 0, 0},
-		{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET, R_03001C_RESOURCE0_WORD7, 0, 0, 0},
+		{R_030000_RESOURCE0_WORD0, 0, 0, 0},
+		{R_030004_RESOURCE0_WORD1, 0, 0, 0},
+		{R_030008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_03000C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_030010_RESOURCE0_WORD4, 0, 0, 0},
+		{R_030014_RESOURCE0_WORD5, 0, 0, 0},
+		{R_030018_RESOURCE0_WORD6, 0, 0, 0},
+		{R_03001C_RESOURCE0_WORD7, 0, 0, 0},
 	};
 	unsigned nreg = Elements(r600_shader_resource);
 
 	for (int i = 0; i < nreg; i++) {
 		r600_shader_resource[i].offset += offset;
 	}
-	return r600_context_add_block(ctx, r600_shader_resource, nreg);
+	return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET);
 }
 
 /* SHADER SAMPLER R600/R700 */
 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
 {
 	struct r600_reg r600_shader_sampler[] = {
-		{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
-		{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
-		{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
+		{R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
+		{R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
+		{R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
 	};
 	unsigned nreg = Elements(r600_shader_sampler);
 
 	for (int i = 0; i < nreg; i++) {
 		r600_shader_sampler[i].offset += offset;
 	}
-	return r600_context_add_block(ctx, r600_shader_sampler, nreg);
+	return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET);
 }
 
 /* SHADER SAMPLER BORDER R600/R700 */
 static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 offset, unsigned id)
 {
 	struct r600_reg r600_shader_sampler_border[] = {
-		{PKT3_SET_CONFIG_REG, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0},
-		{PKT3_SET_CONFIG_REG, 0, R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
-		{PKT3_SET_CONFIG_REG, 0, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
-		{PKT3_SET_CONFIG_REG, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
-		{PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
+		{R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0, 0},
+		{R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
+		{R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
+		{R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
+		{R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
 	};
 	unsigned nreg = Elements(r600_shader_sampler_border);
 	unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX) * 0x100 + 0x40000 + id * 0x1C;
@@ -478,7 +478,7 @@ static int evergreen_state_sampler_border_init(struct r600_context *ctx, u32 off
 		r600_shader_sampler_border[i].offset -= R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
 		r600_shader_sampler_border[i].offset += fake_offset;
 	}
-	r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
+	r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, 0);
 	if (r) {
 		return r;
 	}
@@ -496,13 +496,12 @@ static int evergreen_loop_const_init(struct r600_context *ctx, u32 offset)
 	int i;
 
 	for (i = 0; i < nreg; i++) {
-		r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
-		r600_loop_consts[i].offset_base = EVERGREEN_LOOP_CONST_OFFSET;
 		r600_loop_consts[i].offset = EVERGREEN_LOOP_CONST_OFFSET + ((offset + i) * 4);
 		r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
 		r600_loop_consts[i].flush_flags = 0;
+		r600_loop_consts[i].flush_mask = 0;
 	}
-	return r600_context_add_block(ctx, r600_loop_consts, nreg);
+	return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, EVERGREEN_LOOP_CONST_OFFSET);
 }
 
 int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
@@ -513,29 +512,23 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 	ctx->radeon = radeon;
 	LIST_INITHEAD(&ctx->query_list);
 
-	/* initialize hash */
-	ctx->hash_size = 19;
-	ctx->hash_shift = 11;
-	for (int i = 0; i < 256; i++) {
-		ctx->range[i].start_offset = i << ctx->hash_shift;
-		ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
-		ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
-		if (ctx->range[i].blocks == NULL) {
-			return -ENOMEM;
-		}
+	ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
+	if (!ctx->range) {
+		r = -ENOMEM;
+		goto out_err;
 	}
 
 	/* add blocks */
 	r = r600_context_add_block(ctx, evergreen_config_reg_list,
-				   Elements(evergreen_config_reg_list));
+				   Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 	if (r)
 		goto out_err;
 	r = r600_context_add_block(ctx, evergreen_context_reg_list,
-				   Elements(evergreen_context_reg_list));
+				   Elements(evergreen_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 	if (r)
 		goto out_err;
 	r = r600_context_add_block(ctx, evergreen_ctl_const_list,
-				   Elements(evergreen_ctl_const_list));
+				   Elements(evergreen_ctl_const_list), PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET);
 	if (r)
 		goto out_err;
 
@@ -588,17 +581,9 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 	/* VS loop const */
 	evergreen_loop_const_init(ctx, 32);
 
-	/* setup block table */
-	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
-	for (int i = 0, c = 0; i < 256; i++) {
-		for (int j = 0; j < (1 << ctx->hash_shift); j++) {
-			if (ctx->range[i].blocks[j]) {
-				assert(c < ctx->nblocks);
-				ctx->blocks[c++] = ctx->range[i].blocks[j];
-				j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
-			}
-		}
-	}
+	r = r600_setup_block_table(ctx);
+	if (r)
+		goto out_err;
 
 	/* allocate cs variables */
 	ctx->nreloc = RADEON_CTX_MAX_PM4;
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 34ea2a6bacb..0618d2329e6 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -66,7 +66,8 @@ static void INLINE r600_context_fence_wraparound(struct r600_context *ctx, unsig
 	}
 }
 
-int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg)
+int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
+			   unsigned opcode, unsigned offset_base)
 {
 	struct r600_block *block;
 	struct r600_range *range;
@@ -102,14 +103,20 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 		ctx->nblocks++;
 		for (int j = 0; j < n; j++) {
 			range = &ctx->range[CTX_RANGE_ID(ctx, reg[i + j].offset)];
+			/* create block table if it doesn't exist */
+			if (!range->blocks)
+				range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *));
+			if (!range->blocks)
+				return -1;
+
 			range->blocks[CTX_BLOCK_ID(ctx, reg[i + j].offset)] = block;
 		}
 
 		/* initialize block */
 		block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */
 		block->start_offset = reg[i].offset;
-		block->pm4[block->pm4_ndwords++] = PKT3(reg[i].opcode, n, 0);
-		block->pm4[block->pm4_ndwords++] = (block->start_offset - reg[i].offset_base) >> 2;
+		block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0);
+		block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2;
 		block->reg = &block->pm4[block->pm4_ndwords];
 		block->pm4_ndwords += n;
 		block->nreg = n;
@@ -155,427 +162,427 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 
 /* R600/R700 configuration */
 static const struct r600_reg r600_config_reg_list[] = {
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C00_SQ_CONFIG, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009508_TA_CNTL_AUX, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009714_VC_ENHANCE, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009830_DB_DEBUG, 0, 0, 0},
-	{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_009838_DB_WATERMARKS, 0, 0, 0},
+	{R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0},
+	{R_008C00_SQ_CONFIG, 0, 0, 0},
+	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, 0, 0, 0},
+	{R_008C08_SQ_GPR_RESOURCE_MGMT_2, 0, 0, 0},
+	{R_008C0C_SQ_THREAD_RESOURCE_MGMT, 0, 0, 0},
+	{R_008C10_SQ_STACK_RESOURCE_MGMT_1, 0, 0, 0},
+	{R_008C14_SQ_STACK_RESOURCE_MGMT_2, 0, 0, 0},
+	{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0, 0, 0},
+	{R_009508_TA_CNTL_AUX, 0, 0, 0},
+	{R_009714_VC_ENHANCE, 0, 0, 0},
+	{R_009830_DB_DEBUG, 0, 0, 0},
+	{R_009838_DB_WATERMARKS, 0, 0, 0},
 };
 
 static const struct r600_reg r600_ctl_const_list[] = {
-	{PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
-	{PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET, R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
+	{R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0},
+	{R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0},
 };
 
 static const struct r600_reg r600_context_reg_list[] = {
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028350_SX_MISC, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A14_VGT_HOS_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A40_VGT_GS_MODE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028060_CB_COLOR0_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028080_CB_COLOR0_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028100_CB_COLOR0_MASK, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028064_CB_COLOR1_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028084_CB_COLOR1_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028104_CB_COLOR1_MASK, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028068_CB_COLOR2_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028088_CB_COLOR2_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028108_CB_COLOR2_MASK, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02810C_CB_COLOR3_MASK, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028070_CB_COLOR4_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028090_CB_COLOR4_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028110_CB_COLOR4_MASK, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028074_CB_COLOR5_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028094_CB_COLOR5_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028114_CB_COLOR5_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028078_CB_COLOR6_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028098_CB_COLOR6_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028118_CB_COLOR6_MASK, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02811C_CB_COLOR7_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028120_CB_CLEAR_RED, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028124_CB_CLEAR_GREEN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028128_CB_CLEAR_BLUE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02823C_CB_SHADER_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028238_CB_TARGET_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028414_CB_BLEND_RED, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028418_CB_BLEND_GREEN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02841C_CB_BLEND_BLUE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028420_CB_BLEND_ALPHA, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028424_CB_FOG_RED, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028428_CB_FOG_GREEN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02842C_CB_FOG_BLUE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028430_DB_STENCILREFMASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028438_SX_ALPHA_REF, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028804_CB_BLEND_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028808_CB_COLOR_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C38_CB_CLRCMP_DST, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C48_PA_SC_AA_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028000_DB_DEPTH_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028004_DB_DEPTH_VIEW, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028230_PA_SC_EDGERULE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E20_PA_CL_UCP0_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E30_PA_CL_UCP1_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E40_PA_CL_UCP2_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E50_PA_CL_UCP3_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E60_PA_CL_UCP4_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E70_PA_CL_UCP5_X, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0286D8_SPI_INPUT_Z, 0, 0, 0},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
-	{0, 0, GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028408_VGT_INDX_OFFSET, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
-	{PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
+	{R_028350_SX_MISC, 0, 0, 0},
+	{R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0},
+	{R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0},
+	{R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0},
+	{R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0},
+	{R_028A14_VGT_HOS_CNTL, 0, 0, 0},
+	{R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0},
+	{R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0},
+	{R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0},
+	{R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0},
+	{R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0},
+	{R_028A2C_VGT_GROUP_DECR, 0, 0, 0},
+	{R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0},
+	{R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0},
+	{R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0},
+	{R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0},
+	{R_028A40_VGT_GS_MODE, 0, 0, 0},
+	{R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0},
+	{R_028AB0_VGT_STRMOUT_EN, 0, 0, 0},
+	{R_028AB4_VGT_REUSE_OFF, 0, 0, 0},
+	{R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0},
+	{R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0},
+	{R_028028_DB_STENCIL_CLEAR, 0, 0, 0},
+	{R_02802C_DB_DEPTH_CLEAR, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028060_CB_COLOR0_SIZE, 0, 0, 0},
+	{R_028080_CB_COLOR0_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028100_CB_COLOR0_MASK, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028064_CB_COLOR1_SIZE, 0, 0, 0},
+	{R_028084_CB_COLOR1_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028104_CB_COLOR1_MASK, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028068_CB_COLOR2_SIZE, 0, 0, 0},
+	{R_028088_CB_COLOR2_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028108_CB_COLOR2_MASK, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_02806C_CB_COLOR3_SIZE, 0, 0, 0},
+	{R_02808C_CB_COLOR3_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_02810C_CB_COLOR3_MASK, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028070_CB_COLOR4_SIZE, 0, 0, 0},
+	{R_028090_CB_COLOR4_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028110_CB_COLOR4_MASK, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028074_CB_COLOR5_SIZE, 0, 0, 0},
+	{R_028094_CB_COLOR5_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028114_CB_COLOR5_MASK, 0, 0, 0},
+	{R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0},
+	{R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_028078_CB_COLOR6_SIZE, 0, 0, 0},
+	{R_028098_CB_COLOR6_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_028118_CB_COLOR6_MASK, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF},
+	{R_02807C_CB_COLOR7_SIZE, 0, 0, 0},
+	{R_02809C_CB_COLOR7_VIEW, 0, 0, 0},
+	{R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0},
+	{R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0},
+	{R_02811C_CB_COLOR7_MASK, 0, 0, 0},
+	{R_028120_CB_CLEAR_RED, 0, 0, 0},
+	{R_028124_CB_CLEAR_GREEN, 0, 0, 0},
+	{R_028128_CB_CLEAR_BLUE, 0, 0, 0},
+	{R_02812C_CB_CLEAR_ALPHA, 0, 0, 0},
+	{R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
+	{R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0},
+	{R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{R_02823C_CB_SHADER_MASK, 0, 0, 0},
+	{R_028238_CB_TARGET_MASK, 0, 0, 0},
+	{R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0},
+	{R_028414_CB_BLEND_RED, 0, 0, 0},
+	{R_028418_CB_BLEND_GREEN, 0, 0, 0},
+	{R_02841C_CB_BLEND_BLUE, 0, 0, 0},
+	{R_028420_CB_BLEND_ALPHA, 0, 0, 0},
+	{R_028424_CB_FOG_RED, 0, 0, 0},
+	{R_028428_CB_FOG_GREEN, 0, 0, 0},
+	{R_02842C_CB_FOG_BLUE, 0, 0, 0},
+	{R_028430_DB_STENCILREFMASK, 0, 0, 0},
+	{R_028434_DB_STENCILREFMASK_BF, 0, 0, 0},
+	{R_028438_SX_ALPHA_REF, 0, 0, 0},
+	{R_0286DC_SPI_FOG_CNTL, 0, 0, 0},
+	{R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0},
+	{R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0},
+	{R_028780_CB_BLEND0_CONTROL, 0, 0, 0},
+	{R_028784_CB_BLEND1_CONTROL, 0, 0, 0},
+	{R_028788_CB_BLEND2_CONTROL, 0, 0, 0},
+	{R_02878C_CB_BLEND3_CONTROL, 0, 0, 0},
+	{R_028790_CB_BLEND4_CONTROL, 0, 0, 0},
+	{R_028794_CB_BLEND5_CONTROL, 0, 0, 0},
+	{R_028798_CB_BLEND6_CONTROL, 0, 0, 0},
+	{R_02879C_CB_BLEND7_CONTROL, 0, 0, 0},
+	{R_0287A0_CB_SHADER_CONTROL, 0, 0, 0},
+	{R_028800_DB_DEPTH_CONTROL, 0, 0, 0},
+	{R_028804_CB_BLEND_CONTROL, 0, 0, 0},
+	{R_028808_CB_COLOR_CONTROL, 0, 0, 0},
+	{R_02880C_DB_SHADER_CONTROL, 0, 0, 0},
+	{R_028C04_PA_SC_AA_CONFIG, 0, 0, 0},
+	{R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0},
+	{R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0},
+	{R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0},
+	{R_028C34_CB_CLRCMP_SRC, 0, 0, 0},
+	{R_028C38_CB_CLRCMP_DST, 0, 0, 0},
+	{R_028C3C_CB_CLRCMP_MSK, 0, 0, 0},
+	{R_028C48_PA_SC_AA_MASK, 0, 0, 0},
+	{R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0},
+	{R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0},
+	{R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0},
+	{R_028000_DB_DEPTH_SIZE, 0, 0, 0},
+	{R_028004_DB_DEPTH_VIEW, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0},
+	{R_028D0C_DB_RENDER_CONTROL, 0, 0, 0},
+	{R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0},
+	{R_028D24_DB_HTILE_SURFACE, 0, 0, 0},
+	{R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0},
+	{R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0},
+	{R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0},
+	{R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0},
+	{R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0},
+	{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0},
+	{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0},
+	{R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0},
+	{R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0},
+	{R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0},
+	{R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0},
+	{R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0},
+	{R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0},
+	{R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0},
+	{R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0},
+	{R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0},
+	{R_028230_PA_SC_EDGERULE, 0, 0, 0},
+	{R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0},
+	{R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0},
+	{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0},
+	{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0},
+	{R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0},
+	{R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0},
+	{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0},
+	{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0},
+	{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0},
+	{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0},
+	{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0},
+	{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0},
+	{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0},
+	{R_028810_PA_CL_CLIP_CNTL, 0, 0, 0},
+	{R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0},
+	{R_028818_PA_CL_VTE_CNTL, 0, 0, 0},
+	{R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0},
+	{R_028820_PA_CL_NANINF_CNTL, 0, 0, 0},
+	{R_028A00_PA_SU_POINT_SIZE, 0, 0, 0},
+	{R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0},
+	{R_028A08_PA_SU_LINE_CNTL, 0, 0, 0},
+	{R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0},
+	{R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0},
+	{R_028C00_PA_SC_LINE_CNTL, 0, 0, 0},
+	{R_028C08_PA_SU_VTX_CNTL, 0, 0, 0},
+	{R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0},
+	{R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0},
+	{R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0},
+	{R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0},
+	{R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0},
+	{R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0},
+	{R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0},
+	{R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0},
+	{R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0},
+	{R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0},
+	{R_028E20_PA_CL_UCP0_X, 0, 0, 0},
+	{R_028E24_PA_CL_UCP0_Y, 0, 0, 0},
+	{R_028E28_PA_CL_UCP0_Z, 0, 0, 0},
+	{R_028E2C_PA_CL_UCP0_W, 0, 0, 0},
+	{R_028E30_PA_CL_UCP1_X, 0, 0, 0},
+	{R_028E34_PA_CL_UCP1_Y, 0, 0, 0},
+	{R_028E38_PA_CL_UCP1_Z, 0, 0, 0},
+	{R_028E3C_PA_CL_UCP1_W, 0, 0, 0},
+	{R_028E40_PA_CL_UCP2_X, 0, 0, 0},
+	{R_028E44_PA_CL_UCP2_Y, 0, 0, 0},
+	{R_028E48_PA_CL_UCP2_Z, 0, 0, 0},
+	{R_028E4C_PA_CL_UCP2_W, 0, 0, 0},
+	{R_028E50_PA_CL_UCP3_X, 0, 0, 0},
+	{R_028E54_PA_CL_UCP3_Y, 0, 0, 0},
+	{R_028E58_PA_CL_UCP3_Z, 0, 0, 0},
+	{R_028E5C_PA_CL_UCP3_W, 0, 0, 0},
+	{R_028E60_PA_CL_UCP4_X, 0, 0, 0},
+	{R_028E64_PA_CL_UCP4_Y, 0, 0, 0},
+	{R_028E68_PA_CL_UCP4_Z, 0, 0, 0},
+	{R_028E6C_PA_CL_UCP4_W, 0, 0, 0},
+	{R_028E70_PA_CL_UCP5_X, 0, 0, 0},
+	{R_028E74_PA_CL_UCP5_Y, 0, 0, 0},
+	{R_028E78_PA_CL_UCP5_Z, 0, 0, 0},
+	{R_028E7C_PA_CL_UCP5_W, 0, 0, 0},
+	{R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0},
+	{R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0},
+	{R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0},
+	{R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0},
+	{R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0},
+	{R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0},
+	{R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0},
+	{R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0},
+	{R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0},
+	{R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0},
+	{R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0},
+	{R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0},
+	{R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0},
+	{R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0},
+	{R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0},
+	{R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0},
+	{R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0},
+	{R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0},
+	{R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0},
+	{R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0},
+	{R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0},
+	{R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0},
+	{R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0},
+	{R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0},
+	{R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0},
+	{R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0},
+	{R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0},
+	{R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0},
+	{R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0},
+	{R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0},
+	{R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0},
+	{R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0},
+	{R_028614_SPI_VS_OUT_ID_0, 0, 0, 0},
+	{R_028618_SPI_VS_OUT_ID_1, 0, 0, 0},
+	{R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0},
+	{R_028620_SPI_VS_OUT_ID_3, 0, 0, 0},
+	{R_028624_SPI_VS_OUT_ID_4, 0, 0, 0},
+	{R_028628_SPI_VS_OUT_ID_5, 0, 0, 0},
+	{R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0},
+	{R_028630_SPI_VS_OUT_ID_7, 0, 0, 0},
+	{R_028634_SPI_VS_OUT_ID_8, 0, 0, 0},
+	{R_028638_SPI_VS_OUT_ID_9, 0, 0, 0},
+	{R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0},
+	{R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0},
+	{R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0},
+	{R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0},
+	{R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0},
+	{R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0},
+	{R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0},
+	{R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0},
+	{R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0},
+	{R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0},
+	{R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0},
+	{R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0},
+	{R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0},
+	{R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0},
+	{R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0},
+	{R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0},
+	{R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0},
+	{R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0},
+	{R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0},
+	{R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0},
+	{R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0},
+	{R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0},
+	{R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0},
+	{R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0},
+	{R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0},
+	{R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0},
+	{R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0},
+	{R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0},
+	{R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0},
+	{R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0},
+	{R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0},
+	{R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0},
+	{R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0},
+	{R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0},
+	{R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0},
+	{R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0},
+	{R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0},
+	{R_0286D8_SPI_INPUT_Z, 0, 0, 0},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF},
+	{GROUP_FORCE_NEW_BLOCK, 0, 0, 0},
+	{R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0},
+	{R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0},
+	{R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0},
+	{R_028400_VGT_MAX_VTX_INDX, 0, 0, 0},
+	{R_028404_VGT_MIN_VTX_INDX, 0, 0, 0},
+	{R_028408_VGT_INDX_OFFSET, 0, 0, 0},
+	{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0},
+	{R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0},
+	{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0},
+	{R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0},
+	{R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0},
 };
 
 /* SHADER RESOURCE R600/R700 */
 static int r600_state_resource_init(struct r600_context *ctx, u32 offset)
 {
 	struct r600_reg r600_shader_resource[] = {
-		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038000_RESOURCE0_WORD0, 0, 0, 0},
-		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038004_RESOURCE0_WORD1, 0, 0, 0},
-		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
-		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
-		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038010_RESOURCE0_WORD4, 0, 0, 0},
-		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038014_RESOURCE0_WORD5, 0, 0, 0},
-		{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET, R_038018_RESOURCE0_WORD6, 0, 0, 0},
+		{R_038000_RESOURCE0_WORD0, 0, 0, 0},
+		{R_038004_RESOURCE0_WORD1, 0, 0, 0},
+		{R_038008_RESOURCE0_WORD2, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_03800C_RESOURCE0_WORD3, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF},
+		{R_038010_RESOURCE0_WORD4, 0, 0, 0},
+		{R_038014_RESOURCE0_WORD5, 0, 0, 0},
+		{R_038018_RESOURCE0_WORD6, 0, 0, 0},
 	};
 	unsigned nreg = Elements(r600_shader_resource);
 
 	for (int i = 0; i < nreg; i++) {
 		r600_shader_resource[i].offset += offset;
 	}
-	return r600_context_add_block(ctx, r600_shader_resource, nreg);
+	return r600_context_add_block(ctx, r600_shader_resource, nreg, PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET);
 }
 
 /* SHADER SAMPLER R600/R700 */
 static int r600_state_sampler_init(struct r600_context *ctx, u32 offset)
 {
 	struct r600_reg r600_shader_sampler[] = {
-		{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
-		{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
-		{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
+		{R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0},
+		{R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0},
+		{R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0},
 	};
 	unsigned nreg = Elements(r600_shader_sampler);
 
 	for (int i = 0; i < nreg; i++) {
 		r600_shader_sampler[i].offset += offset;
 	}
-	return r600_context_add_block(ctx, r600_shader_sampler, nreg);
+	return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET);
 }
 
 /* SHADER SAMPLER BORDER R600/R700 */
 static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset)
 {
 	struct r600_reg r600_shader_sampler_border[] = {
-		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
-		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
-		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
-		{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
+		{R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0},
+		{R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0},
+		{R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0},
+		{R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0},
 	};
 	unsigned nreg = Elements(r600_shader_sampler_border);
 
 	for (int i = 0; i < nreg; i++) {
 		r600_shader_sampler_border[i].offset += offset;
 	}
-	return r600_context_add_block(ctx, r600_shader_sampler_border, nreg);
+	return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
 }
 
 static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
@@ -585,14 +592,12 @@ static int r600_loop_const_init(struct r600_context *ctx, u32 offset)
 	int i;
 
 	for (i = 0; i < nreg; i++) {
-		r600_loop_consts[i].opcode = PKT3_SET_LOOP_CONST;
-		r600_loop_consts[i].offset_base = R600_LOOP_CONST_OFFSET;
 		r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4);
 		r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS;
 		r600_loop_consts[i].flush_flags = 0;
 		r600_loop_consts[i].flush_mask = 0;
 	}
-	return r600_context_add_block(ctx, r600_loop_consts, nreg);
+	return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET);
 }
 
 static void r600_context_clear_fenced_bo(struct r600_context *ctx)
@@ -612,8 +617,10 @@ void r600_context_fini(struct r600_context *ctx)
 	struct r600_block *block;
 	struct r600_range *range;
 
-	for (int i = 0; i < 256; i++) {
-		for (int j = 0; j < (1 << ctx->hash_shift); j++) {
+	for (int i = 0; i < NUM_RANGES; i++) {
+		if (!ctx->range[i].blocks)
+			continue;
+		for (int j = 0; j < (1 << HASH_SHIFT); j++) {
 			block = ctx->range[i].blocks[j];
 			if (block) {
 				for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) {
@@ -628,6 +635,7 @@ void r600_context_fini(struct r600_context *ctx)
 		}
 		free(ctx->range[i].blocks);
 	}
+	free(ctx->range);
 	free(ctx->blocks);
 	free(ctx->reloc);
 	free(ctx->bo);
@@ -637,6 +645,36 @@ void r600_context_fini(struct r600_context *ctx)
 	memset(ctx, 0, sizeof(struct r600_context));
 }
 
+int r600_setup_block_table(struct r600_context *ctx)
+{
+	/* setup block table */
+	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
+	if (!ctx->blocks)
+		return -ENOMEM;
+	for (int i = 0, c = 0; i < NUM_RANGES; i++) {
+		if (!ctx->range[i].blocks)
+			continue;
+		for (int j = 0, add; j < (1 << HASH_SHIFT); j++) {
+			if (!ctx->range[i].blocks[j])
+				continue;
+
+			add = 1;
+			for (int k = 0; k < c; k++) {
+				if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
+					add = 0;
+					break;
+				}
+			}
+			if (add) {
+				assert(c < ctx->nblocks);
+				ctx->blocks[c++] = ctx->range[i].blocks[j];
+				j += (ctx->range[i].blocks[j]->nreg) - 1;
+			}
+		}
+	}
+	return 0;
+}
+
 int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 {
 	int r;
@@ -645,30 +683,23 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 	ctx->radeon = radeon;
 	LIST_INITHEAD(&ctx->query_list);
 
-	/* initialize hash */
-	ctx->hash_size = 19;
-	ctx->hash_shift = 11;
-	for (int i = 0; i < 256; i++) {
-		ctx->range[i].start_offset = i << ctx->hash_shift;
-		ctx->range[i].end_offset = ((i + 1) << ctx->hash_shift) - 1;
-		ctx->range[i].blocks = calloc(1 << ctx->hash_shift, sizeof(void*));
-		if (ctx->range[i].blocks == NULL) {
-			r = -ENOMEM;
-			goto out_err;
-		}
+	ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range));
+	if (!ctx->range) {
+		r = -ENOMEM;
+		goto out_err;
 	}
 
 	/* add blocks */
 	r = r600_context_add_block(ctx, r600_config_reg_list,
-				   Elements(r600_config_reg_list));
+				   Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
 	if (r)
 		goto out_err;
 	r = r600_context_add_block(ctx, r600_context_reg_list,
-				   Elements(r600_context_reg_list));
+				   Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
 	if (r)
 		goto out_err;
 	r = r600_context_add_block(ctx, r600_ctl_const_list,
-				   Elements(r600_ctl_const_list));
+				   Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET);
 	if (r)
 		goto out_err;
 
@@ -721,26 +752,9 @@ int r600_context_init(struct r600_context *ctx, struct radeon *radeon)
 	/* VS loop const */
 	r600_loop_const_init(ctx, 32);
 
-	/* setup block table */
-	ctx->blocks = calloc(ctx->nblocks, sizeof(void*));
-	for (int i = 0, c = 0; i < 256; i++) {
-		for (int j = 0, add; j < (1 << ctx->hash_shift); j++) {
-			if (ctx->range[i].blocks[j]) {
-				add = 1;
-				for (int k = 0; k < c; k++) {
-					if (ctx->blocks[k] == ctx->range[i].blocks[j]) {
-						add = 0;
-						break;
-					}
-				}
-				if (add) {
-					assert(c < ctx->nblocks);
-					ctx->blocks[c++] = ctx->range[i].blocks[j];
-					j += (ctx->range[i].blocks[j]->nreg << 2) - 1;
-				}
-			}
-		}
-	}
+	r = r600_setup_block_table(ctx);
+	if (r)
+		goto out_err;
 
 	/* allocate cs variables */
 	ctx->nreloc = RADEON_CTX_MAX_PM4;
@@ -810,12 +824,17 @@ void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
 	     G_0085F0_DB_ACTION_ENA(flush_flags))) {
 		if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) {
 			/* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */
-			if (ctx->radeon->family == CHIP_RV670) {
-				ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
-				ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1);     /* CP_COHER_CNTL */
-				ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff;      /* CP_COHER_SIZE */
-				ctx->pm4[ctx->pm4_cdwords++] = 0;               /* CP_COHER_BASE */
-				ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;      /* POLL_INTERVAL */
+			if ((bo->binding & BO_BOUND_TEXTURE) &&
+			    (flush_flags & S_0085F0_CB_ACTION_ENA(1))) {
+				if ((ctx->radeon->family == CHIP_RV670) ||
+				    (ctx->radeon->family == CHIP_RS780) ||
+				    (ctx->radeon->family == CHIP_RS880)) {
+					ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing);
+					ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1);     /* CP_COHER_CNTL */
+					ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff;      /* CP_COHER_SIZE */
+					ctx->pm4[ctx->pm4_cdwords++] = 0;               /* CP_COHER_BASE */
+					ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;      /* POLL_INTERVAL */
+				}
 			}
 
 			ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing);
@@ -906,16 +925,17 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat
 	int dirty;
 	for (int i = 0; i < state->nregs; i++) {
 		unsigned id, reloc_id;
+		struct r600_pipe_reg *reg = &state->regs[i];
 
-		range = &ctx->range[CTX_RANGE_ID(ctx, state->regs[i].offset)];
-		block = range->blocks[CTX_BLOCK_ID(ctx, state->regs[i].offset)];
-		id = (state->regs[i].offset - block->start_offset) >> 2;
+		range = &ctx->range[CTX_RANGE_ID(ctx, reg->offset)];
+		block = range->blocks[CTX_BLOCK_ID(ctx, reg->offset)];
+		id = (reg->offset - block->start_offset) >> 2;
 
 		dirty = block->status & R600_BLOCK_STATUS_DIRTY;
 
 		new_val = block->reg[id];
-		new_val &= ~state->regs[i].mask;
-		new_val |= state->regs[i].value;
+		new_val &= ~reg->mask;
+		new_val |= reg->value;
 		if (new_val != block->reg[id]) {
 			block->reg[id] = new_val;
 			dirty |= R600_BLOCK_STATUS_DIRTY;
@@ -925,8 +945,8 @@ void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_stat
 		if (block->pm4_bo_index[id] && state->regs[i].bo) {
 			/* find relocation */
 			reloc_id = block->pm4_bo_index[id];
-			r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, state->regs[i].bo);
-			state->regs[i].bo->fence = ctx->radeon->fence;
+			r600_bo_reference(ctx->radeon, &block->reloc[reloc_id].bo, reg->bo);
+			reg->bo->fence = ctx->radeon->fence;
 			/* always force dirty for relocs for now */
 			dirty |= R600_BLOCK_STATUS_DIRTY;
 		}
@@ -947,6 +967,9 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
 	block = range->blocks[CTX_BLOCK_ID(ctx, offset)];
 	if (state == NULL) {
 		block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY);
+		if (block->reloc[1].bo)
+			block->reloc[1].bo->bo->binding &= ~BO_BOUND_TEXTURE;
+
 		r600_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL);
 		r600_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL);
 		LIST_DELINIT(&block->list);
@@ -1000,6 +1023,7 @@ void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_
 			r600_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo);
 			state->regs[2].bo->fence = ctx->radeon->fence;
 			state->regs[3].bo->fence = ctx->radeon->fence;
+			state->regs[2].bo->bo->binding |= BO_BOUND_TEXTURE;
 		}
 	}
 	r600_context_dirty_block(ctx, block, dirty, num_regs - 1);
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h b/src/gallium/winsys/r600/drm/r600_priv.h
index f8363f9272b..4f7e60c3413 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -67,14 +67,13 @@ struct radeon {
 #define REG_FLAG_RV6XX_SBU 4
 
 struct r600_reg {
-	unsigned			opcode;
-	unsigned			offset_base;
 	unsigned			offset;
 	unsigned			flags;
 	unsigned			flush_flags;
 	unsigned			flush_mask;
 };
 
+#define BO_BOUND_TEXTURE 1
 struct radeon_bo {
 	struct pipe_reference		reference;
 	unsigned			handle;
@@ -90,6 +89,7 @@ struct radeon_bo {
 	unsigned			reloc_id;
 	unsigned			last_flush;
 	unsigned                        name;
+	unsigned                        binding;
 };
 
 struct r600_bo {
@@ -145,6 +145,7 @@ int radeon_bo_get_tiling_flags(struct radeon *radeon,
 int radeon_bo_get_name(struct radeon *radeon,
 		       struct radeon_bo *bo,
 		       uint32_t *name);
+int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo);
 
 /*
  * r600_hw_context.c
@@ -154,12 +155,13 @@ void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct r600_bo *r
 void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
 				unsigned flush_mask, struct r600_bo *rbo);
 struct r600_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset);
-int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg);
+int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg,
+			   unsigned opcode, unsigned offset_base);
 void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset);
 void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block);
 void r600_context_dirty_block(struct r600_context *ctx, struct r600_block *block,
 			      int dirty, int index);
-
+int r600_setup_block_table(struct r600_context *ctx);
 void r600_context_reg(struct r600_context *ctx,
 		      unsigned offset, unsigned value,
 		      unsigned mask);
@@ -184,14 +186,25 @@ struct r600_bo *r600_bomgr_bo_create(struct r600_bomgr *mgr,
 /*
  * helpers
  */
-#define CTX_RANGE_ID(ctx, offset) (((offset) >> (ctx)->hash_shift) & 255)
-#define CTX_BLOCK_ID(ctx, offset) ((offset) & ((1 << (ctx)->hash_shift) - 1))
+
+/* each range covers 9 bits of dword space = 512 dwords = 2k bytes */
+/* there is a block entry for each register so 512 blocks */
+/* we have no registers to read/write below 0x8000 (0x2000 in dw space) */
+/* we use some fake offsets at 0x40000 to do evergreen sampler borders so take 0x42000 as a max bound*/
+#define RANGE_OFFSET_START 0x8000
+#define HASH_SHIFT 9
+#define NUM_RANGES (0x42000 - RANGE_OFFSET_START) / (4 << HASH_SHIFT) /* 128 << 9 = 64k */
+
+#define CTX_RANGE_ID(ctx, offset) ((((offset - RANGE_OFFSET_START) >> 2) >> HASH_SHIFT) & 255)
+#define CTX_BLOCK_ID(ctx, offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1))
 
 /*
  * radeon_bo.c
  */
 static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo)
 {
+	if (bo->map_count == 0 && !bo->data)
+		return radeon_bo_fixed_map(radeon, bo);
 	bo->map_count++;
 	return 0;
 }
diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c b/src/gallium/winsys/r600/drm/radeon_bo.c
index 13b1d50b6e5..cd817fc240b 100644
--- a/src/gallium/winsys/r600/drm/radeon_bo.c
+++ b/src/gallium/winsys/r600/drm/radeon_bo.c
@@ -33,7 +33,7 @@
 #include "xf86drm.h"
 #include "radeon_drm.h"
 
-static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo)
+int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo)
 {
 	struct drm_radeon_gem_mmap args;
 	void *ptr;
@@ -64,8 +64,10 @@ static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo)
 
 static void radeon_bo_fixed_unmap(struct radeon *radeon, struct radeon_bo *bo)
 {
-	munmap(bo->data, bo->size);
-	bo->data = NULL;
+	if (bo->data) {
+		munmap(bo->data, bo->size);
+		bo->data = NULL;
+	}
 }
 
 struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
@@ -127,11 +129,6 @@ struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
 			return NULL;
 		}
 	}
-	if (radeon_bo_fixed_map(radeon, bo)) {
-		R600_ERR("failed to map bo\n");
-		radeon_bo_reference(radeon, &bo, NULL);
-		return bo;
-	}
 
 	if (handle)
 		util_hash_table_set(radeon->bo_handles, (void *)(uintptr_t)handle, bo);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 37f6d18689d..3ac57d25b5e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -48,22 +48,59 @@
 #define RADEON_INFO_WANT_CMASK 8
 #endif
 
-/* Enable/disable feature access. Return TRUE on success. */
-static boolean radeon_set_fd_access(int fd, unsigned request, boolean enable)
+/* Enable/disable feature access for one command stream.
+ * If enable == TRUE, return TRUE on success.
+ * Otherwise, return FALSE.
+ *
+ * We basically do the same thing kernel does, because we have to deal
+ * with multiple contexts (here command streams) backed by one winsys. */
+static boolean radeon_set_fd_access(struct radeon_drm_cs *applier,
+                                    struct radeon_drm_cs **owner,
+                                    pipe_mutex *mutex,
+                                    unsigned request, boolean enable)
 {
     struct drm_radeon_info info = {0};
     unsigned value = enable ? 1 : 0;
 
+    pipe_mutex_lock(*mutex);
+
+    /* Early exit if we are sure the request will fail. */
+    if (enable) {
+        if (*owner) {
+            pipe_mutex_unlock(*mutex);
+            return FALSE;
+        }
+    } else {
+        if (*owner != applier) {
+            pipe_mutex_unlock(*mutex);
+            return FALSE;
+        }
+    }
+
+    /* Pass through the request to the kernel. */
     info.value = (unsigned long)&value;
     info.request = request;
-
-    if (drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, sizeof(info)) != 0)
+    if (drmCommandWriteRead(applier->ws->fd, DRM_RADEON_INFO,
+                            &info, sizeof(info)) != 0) {
+        pipe_mutex_unlock(*mutex);
         return FALSE;
+    }
 
-    if (enable && !value)
-        return FALSE;
+    /* Update the rights in the winsys. */
+    if (enable) {
+        if (value) {
+            *owner = applier;
+            fprintf(stderr, "radeon: Acquired Hyper-Z.\n");
+            pipe_mutex_unlock(*mutex);
+            return TRUE;
+        }
+    } else {
+        *owner = NULL;
+        fprintf(stderr, "radeon: Released Hyper-Z.\n");
+    }
 
-    return TRUE;
+    pipe_mutex_unlock(*mutex);
+    return FALSE;
 }
 
 /* Helper function to do the ioctls needed for setup and init. */
@@ -138,16 +175,6 @@ static void do_ioctls(struct radeon_drm_winsys *winsys)
     }
     winsys->z_pipes = target;
 
-    if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) {
-        winsys->hyperz = radeon_set_fd_access(winsys->fd,
-                                              RADEON_INFO_WANT_HYPERZ, TRUE);
-    }
-
-    if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
-        winsys->aacompress = radeon_set_fd_access(winsys->fd,
-                                                  RADEON_INFO_WANT_CMASK, TRUE);
-    }
-
     retval = drmCommandWriteRead(winsys->fd, DRM_RADEON_GEM_INFO,
             &gem_info, sizeof(gem_info));
     if (retval) {
@@ -167,6 +194,9 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws)
 {
     struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
 
+    pipe_mutex_destroy(ws->hyperz_owner_mutex);
+    pipe_mutex_destroy(ws->cmask_owner_mutex);
+
     ws->cman->destroy(ws->cman);
     ws->kman->destroy(ws->kman);
     FREE(rws);
@@ -198,14 +228,38 @@ static uint32_t radeon_get_value(struct radeon_winsys *rws,
         return ws->drm_major*100 + ws->drm_minor >= 206;
     case RADEON_VID_DRM_2_8_0:
         return ws->drm_major*100 + ws->drm_minor >= 208;
-    case RADEON_VID_CAN_HYPERZ:
-        return ws->hyperz;
-    case RADEON_VID_CAN_AACOMPRESS:
-        return ws->aacompress;
     }
     return 0;
 }
 
+static boolean radeon_cs_request_feature(struct radeon_winsys_cs *rcs,
+                                         enum radeon_feature_id fid,
+                                         boolean enable)
+{
+    struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
+
+    switch (fid) {
+    case RADEON_FID_HYPERZ_RAM_ACCESS:
+        if (debug_get_bool_option("RADEON_HYPERZ", FALSE)) {
+            return radeon_set_fd_access(cs, &cs->ws->hyperz_owner,
+                                        &cs->ws->hyperz_owner_mutex,
+                                        RADEON_INFO_WANT_HYPERZ, enable);
+        } else {
+            return FALSE;
+        }
+
+    case RADEON_FID_CMASK_RAM_ACCESS:
+        if (debug_get_bool_option("RADEON_CMASK", FALSE)) {
+            return radeon_set_fd_access(cs, &cs->ws->cmask_owner,
+                                        &cs->ws->cmask_owner_mutex,
+                                        RADEON_INFO_WANT_CMASK, enable);
+        } else {
+            return FALSE;
+        }
+    }
+    return FALSE;
+}
+
 struct radeon_winsys *radeon_drm_winsys_create(int fd)
 {
     struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
@@ -231,10 +285,14 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd)
     /* Set functions. */
     ws->base.destroy = radeon_winsys_destroy;
     ws->base.get_value = radeon_get_value;
+    ws->base.cs_request_feature = radeon_cs_request_feature;
 
     radeon_bomgr_init_functions(ws);
     radeon_drm_cs_init_functions(ws);
 
+    pipe_mutex_init(ws->hyperz_owner_mutex);
+    pipe_mutex_init(ws->cmask_owner_mutex);
+
     return &ws->base;
 
 fail:
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
index e1b9493fc10..d5186bc4d17 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
@@ -32,6 +32,8 @@
 
 #include "radeon_winsys.h"
 
+#include "os/os_thread.h"
+
 struct radeon_drm_winsys {
     struct radeon_winsys base;
 
@@ -52,10 +54,10 @@ struct radeon_drm_winsys {
     unsigned drm_minor;
     unsigned drm_patchlevel;
 
-    /* Hyper-Z user */
-    boolean hyperz;
-    /* AA compression (CMask) */
-    boolean aacompress;
+    struct radeon_drm_cs *hyperz_owner;
+    pipe_mutex hyperz_owner_mutex;
+    struct radeon_drm_cs *cmask_owner;
+    pipe_mutex cmask_owner_mutex;
 };
 
 static INLINE struct radeon_drm_winsys *
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index ca0e6624138..3a64e4abc35 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -87,9 +87,11 @@ enum radeon_value_id {
      * - TBD
      */
     RADEON_VID_DRM_2_8_0,
+};
 
-    RADEON_VID_CAN_HYPERZ,     /* ZMask + HiZ */
-    RADEON_VID_CAN_AACOMPRESS, /* CMask */
+enum radeon_feature_id {
+    RADEON_FID_HYPERZ_RAM_ACCESS,     /* ZMask + HiZ */
+    RADEON_FID_CMASK_RAM_ACCESS,
 };
 
 struct radeon_winsys {
@@ -314,6 +316,16 @@ struct radeon_winsys {
      */
     boolean (*cs_is_buffer_referenced)(struct radeon_winsys_cs *cs,
                                        struct radeon_winsys_cs_handle *buf);
+
+    /**
+     * Request access to a feature for a command stream.
+     *
+     * \param cs        A command stream.
+     * \param fid       A winsys buffer.
+     */
+    boolean (*cs_request_feature)(struct radeon_winsys_cs *cs,
+                                  enum radeon_feature_id fid,
+                                  boolean enable);
 };
 
 #endif
diff --git a/src/gallium/winsys/svga/drm/vmw_screen_svga.c b/src/gallium/winsys/svga/drm/vmw_screen_svga.c
index d96b2b97427..c362aa39938 100644
--- a/src/gallium/winsys/svga/drm/vmw_screen_svga.c
+++ b/src/gallium/winsys/svga/drm/vmw_screen_svga.c
@@ -201,6 +201,19 @@ vmw_svga_winsys_destroy(struct svga_winsys_screen *sws)
 }
 
 
+static SVGA3dHardwareVersion
+vmw_svga_winsys_get_hw_version(struct svga_winsys_screen *sws)
+{
+   struct vmw_winsys_screen *vws = vmw_winsys_screen(sws);
+
+   if (!vws->ioctl.fifo_map) {
+      return 0;
+   }
+
+   return vws->ioctl.fifo_map[SVGA_FIFO_3D_HWVERSION];
+}
+
+
 static boolean
 vmw_svga_winsys_get_cap(struct svga_winsys_screen *sws,
                         SVGA3dDevCapIndex index,
@@ -276,6 +289,7 @@ boolean
 vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws)
 {
    vws->base.destroy = vmw_svga_winsys_destroy;
+   vws->base.get_hw_version = vmw_svga_winsys_get_hw_version;
    vws->base.get_cap = vmw_svga_winsys_get_cap;
    vws->base.context_create = vmw_svga_winsys_context_create;
    vws->base.surface_create = vmw_svga_winsys_surface_create;