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authorIlia Mirkin <[email protected]>2017-01-16 14:25:15 -0500
committerIlia Mirkin <[email protected]>2017-01-16 14:45:46 -0500
commit5eeebca12f1c10aecf7eba3ca15744145e6f921e (patch)
tree566095da9d77c4306210c7c9a760ca2a3c056a1d /src/gallium
parent6be4a404300e4896ef531a10e24c6b76698afe1a (diff)
nv50/ir: handle new DDIV op which will be used for double divisions
The existing lowering is in place to lower that to RCP + MUL, or fancier things down the line if necessary. Signed-off-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 86348e711b4..6b38d5f0fa9 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -612,6 +612,7 @@ nv50_ir::DataType Instruction::inferSrcType() const
case TGSI_OPCODE_DNEG:
case TGSI_OPCODE_DADD:
case TGSI_OPCODE_DMUL:
+ case TGSI_OPCODE_DDIV:
case TGSI_OPCODE_DMAX:
case TGSI_OPCODE_DMIN:
case TGSI_OPCODE_DSLT:
@@ -810,6 +811,7 @@ static nv50_ir::operation translateOpcode(uint opcode)
NV50_IR_OPCODE_CASE(DNEG, NEG);
NV50_IR_OPCODE_CASE(DADD, ADD);
NV50_IR_OPCODE_CASE(DMUL, MUL);
+ NV50_IR_OPCODE_CASE(DDIV, DIV);
NV50_IR_OPCODE_CASE(DMAX, MAX);
NV50_IR_OPCODE_CASE(DMIN, MIN);
NV50_IR_OPCODE_CASE(DSLT, SET);
@@ -3745,6 +3747,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
}
case TGSI_OPCODE_DADD:
case TGSI_OPCODE_DMUL:
+ case TGSI_OPCODE_DDIV:
case TGSI_OPCODE_DMAX:
case TGSI_OPCODE_DMIN:
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {