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authorBen Skeggs <[email protected]>2008-06-08 15:51:54 +1000
committerBen Skeggs <[email protected]>2008-06-29 15:46:16 +1000
commit34a039ae7b158cacb5b20d91067e9d6458d30a56 (patch)
treef92b00d5706b90150746e16ff000fac58498d895 /src/gallium
parentafcaeaa0e4dc3ced40621c76304a2c0c5a3ab403 (diff)
nv50: fix src1 & src2 == const
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/nv50/nv50_program.c26
1 files changed, 20 insertions, 6 deletions
diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index b151b540bf4..936a8ef9b35 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -22,8 +22,6 @@
* - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD,
* but can emit to P_TEMP first - then MOV later. NVIDIA does this
*
- * Hmmm.. what happens if we have src1+src2 both consts.. ouch !
- *
* Verify half-insns work where expected - and force disable them where they
* don't work - MUL has it forcibly disabled atm as it fixes POW..
*
@@ -391,8 +389,16 @@ set_src_1(struct nv50_pc *pc, struct nv50_reg *src, unsigned *inst)
src = temp;
} else
if (src->type == P_CONST || src->type == P_IMMD) {
- set_cseg(pc, src, inst);
- inst[0] |= 0x00800000;
+ assert(!(inst[0] & 0x00800000));
+ if (inst[0] & 0x01000000) {
+ struct nv50_reg *temp = temp_temp(pc);
+
+ emit_mov(pc, temp, src);
+ src = temp;
+ } else {
+ set_cseg(pc, src, inst);
+ inst[0] |= 0x00800000;
+ }
}
alloc_reg(pc, src);
@@ -411,8 +417,16 @@ set_src_2(struct nv50_pc *pc, struct nv50_reg *src, unsigned *inst)
src = temp;
} else
if (src->type == P_CONST || src->type == P_IMMD) {
- set_cseg(pc, src, inst);
- inst[0] |= 0x01000000;
+ assert(!(inst[0] & 0x01000000));
+ if (inst[0] & 0x00800000) {
+ struct nv50_reg *temp = temp_temp(pc);
+
+ emit_mov(pc, temp, src);
+ src = temp;
+ } else {
+ set_cseg(pc, src, inst);
+ inst[0] |= 0x01000000;
+ }
}
alloc_reg(pc, src);