diff options
| author | Ilia Mirkin <[email protected]> | 2015-07-28 02:37:51 -0400 |
|---|---|---|
| committer | Ilia Mirkin <[email protected]> | 2015-07-28 02:38:43 -0400 |
| commit | 313940b03cf7c857143b9e3ec0ab969ce4472c83 (patch) | |
| tree | fbfa715558f453f7b4914e2687681d7f57e648e8 /src/gallium | |
| parent | ab63610a3603ae1e40a36d238b5938621bb9e8cc (diff) | |
nvc0/ir: trim out barrier sync for non-compute shaders
It seems like they're never necessary, and actively cause harm. This
fixes some of the barrier-related piglits.
Signed-off-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 710f53de1c4..c632e30afae 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -559,6 +559,12 @@ NVC0LegalizePostRA::visit(BasicBlock *bb) } else if (i->isNop()) { bb->remove(i); + } else + if (i->op == OP_BAR && i->subOp == NV50_IR_SUBOP_BAR_SYNC && + prog->getType() != Program::TYPE_COMPUTE) { + // It seems like barriers are never required for tessellation since + // the warp size is 32, and there are always at most 32 tcs threads. + bb->remove(i); } else { // TODO: Move this to before register allocation for operations that // need the $c register ! |