diff options
| author | Marek Olšák <[email protected]> | 2016-10-28 23:08:50 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-11-15 20:23:40 +0100 |
| commit | 74e39de9324d2d2333cda6adca50ae2a3fc36de2 (patch) | |
| tree | ac3a0f374798aae867746689ce42c023907253f0 /src/gallium | |
| parent | 537b897f51690aa11089bec0d82e89ca712b1469 (diff) | |
radeonsi: set IF_THRESHOLD to 3
Piglit regressions (radeonsi or LLVM bugs, they pass on softpipe):
- glsl-1.10/execution/variable-indexing/vs-output-array-vec3-index-wr
- glsl-1.10/execution/variable-indexing/vs-output-array-vec4-index-wr
- glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-col-row-wr
- glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-row-wr
Totals:
SGPRS: 1132185 -> 1168801 (3.23 %)
VGPRS: 907856 -> 906204 (-0.18 %)
Spilled SGPRs: 2011 -> 2425 (20.59 %)
Spilled VGPRs: 368 -> 96 (-73.91 %)
Scratch VGPRs: 1344 -> 1060 (-21.13 %) dwords per thread
Code Size: 35916164 -> 35705372 (-0.59 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 194010 -> 194921 (0.47 %)
Wait states: 0 -> 0 (0.00 %)
Before:
VGPR SPILLING APPS Shaders SpillVGPR ScratchVGPR
alien_isolation 2938 38 40
bioshock-infinite 1769 245 732
dirt-showdown 548 85 72
f1-2015 776 0 320
ue4_lightroom_inter.. 74 0 180
After:
VGPR SPILLING APPS Shaders SpillVGPR ScratchVGPR
alien_isolation 2938 38 40
bioshock-infinite 1769 0 480
dirt-showdown 548 58 40
f1-2015 776 0 320
ue4_lightroom_inter.. 74 0 180
Bioshock and DiRT benefit.
If I set IF_THRESHOLD=4, tesseract starts spilling VGPRs
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 146128dbc3c..6be676d786a 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -632,6 +632,8 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu return 32; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; + case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: + return 3; /* Supported boolean features. */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: @@ -659,7 +661,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu case PIPE_SHADER_CAP_SUPPORTED_IRS: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: return 0; } return 0; |