diff options
| author | Rob Clark <[email protected]> | 2017-12-03 11:48:56 -0500 |
|---|---|---|
| committer | Rob Clark <[email protected]> | 2017-12-03 14:17:41 -0500 |
| commit | 48eef0c18248db948378ecf9a5f9930fa467ae9f (patch) | |
| tree | 8815668e6036281ee7cd56f64ba3642e83ea8b20 /src/gallium | |
| parent | e6c6495d3a850da9fc04355df40fc8ab8fa80621 (diff) | |
freedreno/ir3: all mem instructions have WAR hazzard
It isn't just load instructions that have write-after-read hazzard.
Fixes stk gaussian blur compute shaders.
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/freedreno/ir3/ir3_legalize.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_legalize.c b/src/gallium/drivers/freedreno/ir3/ir3_legalize.c index 3f12b68ada1..b4d5db58ccb 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_legalize.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_legalize.c @@ -211,7 +211,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block) /* both tex/sfu appear to not always immediately consume * their src register(s): */ - if (is_tex(n) || is_sfu(n) || is_load(n)) { + if (is_tex(n) || is_sfu(n) || is_mem(n)) { foreach_src(reg, n) { if (reg_gpr(reg)) regmask_set(&needs_ss_war, reg); |