radeonsi: enable TGSI support cap for compute shaders

v2: Use chip_class instead of family.

v3: Check kernel version for SI.

v4: Preemptively allow amdgpu winsys for SI.

Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>

2 files changed, 30 insertions, 7 deletions

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index a8660f20c86..9ed6da6a82b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -646,23 +646,34 @@ static int r600_get_compute_param(struct pipe_screen *screen,
 			uint64_t *grid_size = ret;
 			grid_size[0] = 65535;
 			grid_size[1] = 65535;
-			grid_size[2] = 1;
+			grid_size[2] = 65535;
 		}
 		return 3 * sizeof(uint64_t) ;
 
 	case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 		if (ret) {
 			uint64_t *block_size = ret;
-			block_size[0] = 256;
-			block_size[1] = 256;
-			block_size[2] = 256;
+			if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
+			    ir_type == PIPE_SHADER_IR_TGSI) {
+				block_size[0] = 2048;
+				block_size[1] = 2048;
+				block_size[2] = 2048;
+			} else {
+				block_size[0] = 256;
+				block_size[1] = 256;
+				block_size[2] = 256;
+			}
 		}
 		return 3 * sizeof(uint64_t);
 
 	case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 		if (ret) {
 			uint64_t *max_threads_per_block = ret;
-			*max_threads_per_block = 256;
+			if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 &&
+			    ir_type == PIPE_SHADER_IR_TGSI)
+				*max_threads_per_block = 2048;
+			else
+				*max_threads_per_block = 256;
 		}
 		return sizeof(uint64_t);
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index dabd28a4bc2..17d59b60d06 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -473,6 +473,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 {
+	struct si_screen *sscreen = (struct si_screen *)pscreen;
+
 	switch(shader)
 	{
 	case PIPE_SHADER_FRAGMENT:
@@ -490,9 +492,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu
 		case PIPE_SHADER_CAP_PREFERRED_IR:
 			return PIPE_SHADER_IR_NATIVE;
 
-		case PIPE_SHADER_CAP_SUPPORTED_IRS:
-			return 0;
+		case PIPE_SHADER_CAP_SUPPORTED_IRS: {
+			int ir = 1 << PIPE_SHADER_IR_NATIVE;
 
+			/* Old kernels disallowed some register writes for SI
+			 * that are used for indirect dispatches. */
+			if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
+			                           sscreen->b.info.drm_major == 3 ||
+			                           (sscreen->b.info.drm_major == 2 &&
+			                            sscreen->b.info.drm_minor >= 45)))
+				ir |= 1 << PIPE_SHADER_IR_TGSI;
+
+			return ir;
+		}
 		case PIPE_SHADER_CAP_DOUBLES:
 			return HAVE_LLVM >= 0x0307;