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authorEmil Velikov <[email protected]>2014-08-15 17:36:34 +0100
committerEmil Velikov <[email protected]>2014-08-15 17:41:34 +0100
commit139751403c56d965d7c22bceddd34387759075a9 (patch)
tree30d769bdcb59faf21fb31914bd40ef471f6f4aae /src/gallium
parent64b1dc44495890cbc2c7c5509cb830264020998c (diff)
gallium: add GLX_MESA_query_renderer caps
Namely vendor/device id, accelerated and UMA, which will be used to describe the underlying renderer. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/docs/source/screen.rst8
-rw-r--r--src/gallium/include/pipe/p_defines.h5
2 files changed, 13 insertions, 0 deletions
diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst
index 6fecc15d6b8..26949233286 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -215,6 +215,14 @@ The integer capabilities:
See pipe_draw_info.
* ``PIPE_CAP_TGSI_FS_FINE_DERIVATIVE``: Whether the fragment shader supports
the FINE versions of DDX/DDY.
+* ``PIPE_CAP_VENDOR_ID``: The vendor ID of the underlying hardware. If it's
+ not available one should return 0xFFFFFFFF.
+* ``PIPE_CAP_DEVICE_ID``: The device ID (PCI ID) of the underlying hardware.
+ 0xFFFFFFFF if not available.
+* ``PIPE_CAP_ACCELERATED``: Whether the renderer is hardware accelerated.
+* ``PIPE_CAP_VIDEO_MEMORY``: The amount of video memory in megabytes.
+* ``PIPE_CAP_UMA``: If the device has a unified memory architecture or on-card
+ memory and GART.
.. _pipe_capf:
diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h
index 53d5d4b00b5..1a31350fe31 100644
--- a/src/gallium/include/pipe/p_defines.h
+++ b/src/gallium/include/pipe/p_defines.h
@@ -563,6 +563,11 @@ enum pipe_cap {
PIPE_CAP_MAX_VERTEX_STREAMS = 100,
PIPE_CAP_DRAW_INDIRECT = 101,
PIPE_CAP_TGSI_FS_FINE_DERIVATIVE = 102,
+ PIPE_CAP_VENDOR_ID = 103,
+ PIPE_CAP_DEVICE_ID = 104,
+ PIPE_CAP_ACCELERATED = 105,
+ PIPE_CAP_VIDEO_MEMORY = 106,
+ PIPE_CAP_UMA = 107,
};
#define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0)