diff options
| author | Alex Deucher <[email protected]> | 2012-10-23 12:12:34 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2012-10-26 09:33:06 -0400 |
| commit | 67c875117ca2f4bc7eea8cd11ba90e26f79069d7 (patch) | |
| tree | 693744a4213f724ac63898ac791601fb3397058b /src/gallium | |
| parent | d781f0c73cf47aee7f660d9b859a6c473293be62 (diff) | |
r600g: emit some additional regs on cayman
These are common to both evergreen and cayman, but were
not emitted on cayman.
Signed-off-by: Alex Deucher <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_state.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 29e6822a4af..1bf6996327b 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2455,6 +2455,23 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0); + r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0); + r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4)); + + r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6); + r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */ + r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */ + r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */ + r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */ + r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */ + r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */ + + r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4); + r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */ + r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */ + r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */ + r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */ + r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ @@ -2568,6 +2585,43 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); + /* to avoid GPU doing any preloading of constant from random address */ + r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); + r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */ + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + + r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 16); + r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */ + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); if (rctx->screen->has_streamout) { |