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authorRob Clark <[email protected]>2015-04-10 15:57:29 -0400
committerRob Clark <[email protected]>2015-04-11 11:40:57 -0400
commit1b936bb9f8da72baaef5c7454e8bebb63bbe067a (patch)
tree0d0e3b7c3a0c16f825f4486757878bf983003a5f /src/gallium
parent715b2e0dbb88ef80880b8517f8fe822c26ef3be5 (diff)
freedreno/ir3/nir: handle system values
Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c53
1 files changed, 50 insertions, 3 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index f6f44e02af1..34598dbab1c 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -255,9 +255,14 @@ compile_init(struct ir3_shader_variant *so,
if (lowered_tokens != tokens)
free((void *)lowered_tokens);
- so->first_immediate = ctx->s->num_uniforms;
- /* for now, now driver params: */
- so->first_driver_param = so->first_immediate;
+ so->first_driver_param = so->first_immediate = ctx->s->num_uniforms;
+
+ /* one (vec4) slot for vertex id base: */
+ if (so->type == SHADER_VERTEX)
+ so->first_immediate++;
+
+ /* reserve 4 (vec4) slots for ubo base addresses: */
+ so->first_immediate += 4;
return ctx;
}
@@ -1067,6 +1072,22 @@ emit_intrinisic_store_var(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
}
}
+static void add_sysval_input(struct ir3_compile *ctx, unsigned name,
+ struct ir3_instruction *instr)
+{
+ struct ir3_shader_variant *so = ctx->so;
+ unsigned r = regid(so->inputs_count, 0);
+ unsigned n = so->inputs_count++;
+
+ so->inputs[n].semantic = ir3_semantic_name(name, 0);
+ so->inputs[n].compmask = 1;
+ so->inputs[n].regid = r;
+ so->inputs[n].interpolate = TGSI_INTERPOLATE_CONSTANT;
+ so->total_in++;
+
+ ctx->block->inputs[r] = instr;
+}
+
static void
emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
{
@@ -1128,6 +1149,32 @@ emit_intrinisic(struct ir3_compile *ctx, nir_intrinsic_instr *intr)
b->outputs[n] = src[i];
}
break;
+ case nir_intrinsic_load_base_vertex:
+ if (!ctx->basevertex) {
+ /* first four vec4 sysval's reserved for UBOs: */
+ unsigned r = regid(ctx->so->first_driver_param + 4, 0);
+ ctx->basevertex = create_uniform(ctx, r);
+ add_sysval_input(ctx, TGSI_SEMANTIC_BASEVERTEX,
+ ctx->basevertex);
+ }
+ dst[0] = ctx->basevertex;
+ break;
+ case nir_intrinsic_load_vertex_id_zero_base:
+ if (!ctx->vertex_id) {
+ ctx->vertex_id = create_input(ctx->block, NULL, 0);
+ add_sysval_input(ctx, TGSI_SEMANTIC_VERTEXID_NOBASE,
+ ctx->vertex_id);
+ }
+ dst[0] = ctx->vertex_id;
+ break;
+ case nir_intrinsic_load_instance_id:
+ if (!ctx->instance_id) {
+ ctx->instance_id = create_input(ctx->block, NULL, 0);
+ add_sysval_input(ctx, TGSI_SEMANTIC_INSTANCEID,
+ ctx->instance_id);
+ }
+ dst[0] = ctx->instance_id;
+ break;
case nir_intrinsic_discard_if:
case nir_intrinsic_discard: {
struct ir3_instruction *cond, *kill;