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authorDave Airlie <[email protected]>2017-12-27 08:02:30 +1000
committerDave Airlie <[email protected]>2017-12-27 11:10:50 +1000
commitdb27907d78c05f7266d73a26f052e55e9ddde34c (patch)
tree4be67738e8a15b2c4243ee374f92ddfffa5fb77e /src/gallium
parentcf363e440501b5abf37c319c5e2635c664ec5fe1 (diff)
radv/radeonsi: set dcc min uncompressed properly for APUs.
This is ported from amdvlk. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index d2d5dd70ecf..f88bf29e202 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2451,6 +2451,14 @@ static void si_initialize_color_surface(struct si_context *sctx,
if (sctx->b.chip_class >= VI) {
unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
+ unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
+
+ /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
+ 64 for APU because all of our APUs to date use DIMMs which have
+ a request granularity size of 64B while all other chips have a
+ 32B request size */
+ if (!sctx->screen->info.has_dedicated_vram)
+ min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
if (rtex->resource.b.b.nr_samples > 1) {
if (rtex->surface.bpe == 1)
@@ -2460,6 +2468,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
}
surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
+ S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
S_028C78_INDEPENDENT_64B_BLOCKS(1);
}