diff options
| author | Tom Stellard <[email protected]> | 2012-08-02 14:05:20 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-02 20:12:10 +0000 |
| commit | a35eea786823f0130b925cb25486d7d162f2d68c (patch) | |
| tree | 31030cc37d636e7fa7efa58c7be3aebe0729d765 /src/gallium | |
| parent | 4104bae063a3a06ddc00371a576ad0a55f520473 (diff) | |
radeon/llvm: Add support for fneg on SI
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeon/SIISelLowering.cpp | 15 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp index a14cb6f4106..3e08e885129 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.cpp +++ b/src/gallium/drivers/radeon/SIISelLowering.cpp @@ -99,6 +99,21 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( MI->eraseFromParent(); break; + case AMDGPU::FNEG_SI: + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_MOV_B32_e64)) + .addOperand(MI->getOperand(0)) + .addOperand(MI->getOperand(1)) + // VSRC1-2 are unused, but we still need to fill all the + // operand slots, so we just reuse the VSRC0 operand + .addOperand(MI->getOperand(1)) + .addOperand(MI->getOperand(1)) + .addImm(0) // ABS + .addImm(0) // CLAMP + .addImm(0) // OMOD + .addImm(1); // NEG + MI->eraseFromParent(); + break; + case AMDGPU::SI_INTERP: LowerSI_INTERP(MI, *BB, I, MRI); break; diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 1f03ea57278..c753943eabf 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -1017,6 +1017,7 @@ def : Pat < def CLAMP_SI : CLAMP<VReg_32>; def FABS_SI : FABS<VReg_32>; +def FNEG_SI : FNEG<VReg_32>; def : Extract_Element <f32, v4f32, VReg_128, 0, sel_x>; def : Extract_Element <f32, v4f32, VReg_128, 1, sel_y>; |