r600g: use blitter to do db->cb flushing.

use the blitter + custom stage to avoid doing a whole lot of state
setup by hand. This makes life a lot easier for doing this on evergreen
it also keeps all the state setup in one place.

We setup a custom context state at the start with a flag to denote
its for the flush, when it gets generated we generate the correct state
for the flush and no longer have to do it all by hand.

this should also make adding texture *to* depth easier.

8 files changed, 145 insertions, 959 deletions

diff --git a/src/gallium/drivers/r600/eg_hw_states.c b/src/gallium/drivers/r600/eg_hw_states.c
index 6ad350b7d3c..42b49002c39 100644
--- a/src/gallium/drivers/r600/eg_hw_states.c
+++ b/src/gallium/drivers/r600/eg_hw_states.c
@@ -543,17 +543,9 @@ static void eg_resource(struct pipe_context *ctx, struct radeon_state *rstate,
 	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
 	tmp = (struct r600_resource_texture*)view->texture;
 	rbuffer = &tmp->resource;
-	if (tmp->depth) {
-		r = r600_texture_from_depth(ctx, tmp, view->first_level);
-		if (r) {
-			return;
-		}
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], tmp->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], tmp->uncompressed);
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
-	}
+	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
+	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
+
 	rstate->nbo = 2;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
@@ -1015,141 +1007,7 @@ static int eg_vs_shader(struct r600_context *rctx, struct r600_context_state *rp
 	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	state->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
-}
-
-static void eg_texture_state_scissor(struct r600_screen *rscreen,
-					struct r600_resource_texture *rtexture,
-					unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->scissor[level];
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-	rstate->states[EG_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
-	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[EG_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
-
-	radeon_state_pm4(rstate);
-}
-
-static void eg_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	struct radeon_state *rstate;
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype, attrib;
-	const struct util_format_description *desc;
-
-	rstate = &rtexture->cb[cb][level];
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0, cb, 0);
-	rbuffer = &rtexture->resource;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	ntype = 0;
-	attrib = 0;
-	desc = util_format_description(rbuffer->base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_028C70_NUMBER_SRGB;
-	format = r600_translate_colorformat(rtexture->resource.base.b.format);
-	swap = r600_translate_colorswap(rtexture->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 1;
-		color_info = 0;
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 1;
-		color_info = S_028C70_SOURCE_FORMAT(1);
-	}
-	color_info |= S_028C70_FORMAT(format) |
-		S_028C70_COMP_SWAP(swap) |
-		S_028C70_BLEND_CLAMP(1) |
-		S_028C70_NUMBER_TYPE(ntype);
-	rstate->states[EG_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
-	rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
-	rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
-	rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
-
-	radeon_state_pm4(rstate);
-}
-
-static void eg_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->db[level];
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice, format;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
-	rbuffer = &rtexture->resource;
-	rtexture->tiled = 1;
-	rtexture->array_mode = 2;
-	rtexture->tile_type = 1;
-	rtexture->depth = 1;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	format = r600_translate_dbformat(rbuffer->base.b.format);
-	rstate->states[EG_DB__DB_Z_READ_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[EG_DB__DB_Z_WRITE_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[EG_DB__DB_Z_INFO] = S_028040_ARRAY_MODE(rtexture->array_mode) | S_028040_FORMAT(format);
-	rstate->states[EG_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[EG_DB__DB_DEPTH_SIZE] = S_028058_PITCH_TILE_MAX(pitch);
-	rstate->states[EG_DB__DB_DEPTH_SLICE] = S_02805C_SLICE_TILE_MAX(slice);
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 1;
-
-	radeon_state_pm4(rstate);
-}
 
-static void eg_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->viewport[level];
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
-	rstate->states[EG_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
-	rstate->states[EG_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	rstate->states[EG_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-
-	radeon_state_pm4(rstate);
 }
 
 struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
@@ -1171,10 +1029,6 @@ struct r600_context_hw_state_vtbl eg_hw_state_vtbl = {
 	.vs_shader = eg_vs_shader,
 	.ps_shader = eg_ps_shader,
 	.init_config = eg_init_config,
-	.texture_state_viewport = eg_texture_state_viewport,
-	.texture_state_db = eg_texture_state_db,
-	.texture_state_cb = eg_texture_state_cb,
-	.texture_state_scissor = eg_texture_state_scissor,
 };
 
 void eg_set_constant_buffer(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 40422042d3c..0b22f037015 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -136,531 +136,75 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 				  src, subsrc, srcx, srcy, srcz, width, height);
 }
 
-void r600_init_blit_functions(struct r600_context *rctx)
+static void *r600_create_db_flush_dsa(struct r600_context *rctx)
 {
-	rctx->context.clear = r600_clear;
-	rctx->context.clear_render_target = r600_clear_render_target;
-	rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
-	rctx->context.resource_copy_region = r600_resource_copy_region;
-}
-
-
-struct r600_blit_states {
-	struct radeon_state	rasterizer;
-	struct radeon_state	dsa;
-	struct radeon_state	blend;
-	struct radeon_state	cb_cntl;
-	struct radeon_state	vgt;
-	struct radeon_state	draw;
-	struct radeon_state	vs_constant0;
-	struct radeon_state	vs_constant1;
-	struct radeon_state	vs_constant2;
-	struct radeon_state	vs_constant3;
-	struct radeon_state	ps_shader;
-	struct radeon_state	vs_shader;
-	struct radeon_state	vs_resource0;
-	struct radeon_state	vs_resource1;
-	struct radeon_state     cb_flush;
-	struct radeon_state     db_flush;
-};
-
-static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates)
-{
-	struct radeon_state *rstate;
-	struct radeon_ws_bo *bo;
-	void *data;
-	float *vbo;
+	struct r600_screen *rscreen = rctx->screen;
+	struct pipe_depth_stencil_alpha_state dsa;
+	struct r600_context_state *state;
+	boolean quirk = false;
 	enum radeon_family family;
-	float vbo_r600[] = {
-	  -1.0, -1.0, 1.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0,
-	   1.0, -1.0, 1.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0,
-	   1.0,  1.0, 1.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0,
-	  -1.0,  1.0, 1.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0 };
-
-	float vbo_rv6xx[] = {
-	  -1.0, -1.0, 0.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0,
-	   1.0, -1.0, 0.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0,
-	   1.0,  1.0, 0.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0,
-	  -1.0,  1.0, 0.0, 1.0,
-	   0.5,  0.5, 0.0, 0.0};
-
 
 	family = radeon_get_family(rscreen->rw);
-	/* simple shader */
-	bo = radeon_ws_bo(rscreen->rw, 128, 4096, 0);
-	if (bo == NULL) {
-		return -ENOMEM;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, bo, 0, NULL);
-	if (!data) {
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return -ENOMEM;
-	}
 	if (family == CHIP_RV610 || family == CHIP_RV630 || family == CHIP_RV620 ||
 	    family == CHIP_RV635)
-		vbo = vbo_rv6xx;
-	else
-		vbo = vbo_r600;
-
-	memcpy(data, vbo, 128);
-	radeon_ws_bo_unmap(rscreen->rw, bo);
-
-	rstate = &bstates->vs_resource0;
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
-	rstate->bo[0] = bo;
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-		return -ENOMEM;
-	}
-
-	rstate = &bstates->vs_resource1;
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	struct radeon_ws_bo *bo;
-	void *data;
-	u32 shader_bc_r600[] = {
-		0x00000004, 0x81000400,
-		0x00000008, 0xA01C0000,
-		0xC001A03C, 0x94000688,
-		0xC0024000, 0x94200688,
-		0x7C000000, 0x002D1001,
-		0x00080000, 0x00000000,
-		0x7C000100, 0x002D1002,
-		0x00080000, 0x00000000,
-		0x00000001, 0x00601910,
-		0x00000401, 0x20601910,
-		0x00000801, 0x40601910,
-		0x80000C01, 0x60601910,
-		0x00000002, 0x00801910,
-		0x00000402, 0x20801910,
-		0x00000802, 0x40801910,
-		0x80000C02, 0x60801910
-	};
-	u32 shader_bc_r700[] = {
-		0x00000004, 0x81000400,
-		0x00000008, 0xA01C0000,
-		0xC001A03C, 0x94000688,
-		0xC0024000, 0x94200688,
-		0x7C000000, 0x002D1001,
-		0x00080000, 0x00000000,
-		0x7C000100, 0x002D1002,
-		0x00080000, 0x00000000,
-		0x00000001, 0x00600C90,
-		0x00000401, 0x20600C90,
-		0x00000801, 0x40600C90,
-		0x80000C01, 0x60600C90,
-		0x00000002, 0x00800C90,
-		0x00000402, 0x20800C90,
-		0x00000802, 0x40800C90,
-		0x80000C02, 0x60800C90
-	};
-
-	/* simple shader */
-	bo = radeon_ws_bo(rscreen->rw, 128, 4096, 0);
-	if (bo == NULL) {
-		return;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, bo, 0, NULL);
-	if (!data) {
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
-	}
-	switch (radeon_get_family_class(rscreen->rw)) {
-	case R600:
-		memcpy(data, shader_bc_r600, 128);
-		break;
-	case R700:
-		memcpy(data, shader_bc_r700, 128);
-		break;
-	default:
-		R600_ERR("unsupported chip family\n");
-		radeon_ws_bo_unmap(rscreen->rw, bo);
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
-	}
-	radeon_ws_bo_unmap(rscreen->rw, bo);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
+		quirk = true;
+	
+	memset(&dsa, 0, sizeof(dsa));
 
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_0] = 0x03020100;
-	rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_1] = 0x07060504;
-	rstate->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = 0x00000005;
-
-	rstate->bo[0] = bo;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], bo);
-	rstate->nbo = 2;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_ps_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	struct radeon_ws_bo *bo;
-	void *data;
-	u32 shader_bc_r600[] = {
-		0x00000002, 0xA00C0000,
-		0xC0008000, 0x94200688,
-		0x00000000, 0x00201910,
-		0x00000400, 0x20201910,
-		0x00000800, 0x40201910,
-		0x80000C00, 0x60201910
-	};
-	u32 shader_bc_r700[] = {
-		0x00000002, 0xA00C0000,
-		0xC0008000, 0x94200688,
-		0x00000000, 0x00200C90,
-		0x00000400, 0x20200C90,
-		0x00000800, 0x40200C90,
-		0x80000C00, 0x60200C90
-	};
-
-	/* simple shader */
-	bo = radeon_ws_bo(rscreen->rw, 128, 4096, 0);
-	if (bo == NULL) {
-		return;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, bo, 0, NULL);
-	if (!data) {
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
-	}
-	switch (radeon_get_family_class(rscreen->rw)) {
-	case R600:
-		memcpy(data, shader_bc_r600, 48);
-		break;
-	case R700:
-		memcpy(data, shader_bc_r700, 48);
-		break;
-	default:
-		R600_ERR("unsupported chip family\n");
-		radeon_ws_bo_unmap(rscreen->rw, bo);
-		radeon_ws_bo_reference(rscreen->rw, &bo, NULL);
-		return;
+	if (quirk) {
+		dsa.depth.enabled = 1;
+		dsa.depth.func = PIPE_FUNC_LEQUAL;
+		dsa.stencil[0].enabled = 1;
+		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
+		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
+		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
+		dsa.stencil[0].writemask = 0xff;
 	}
-	radeon_ws_bo_unmap(rscreen->rw, bo);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0] = 0x00000C00;
-	rstate->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = 0x10000001;
-	rstate->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
-	rstate->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = 0x00000002;
-
-	rstate->bo[0] = bo;
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_vgt(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VGT, 0, 0);
 
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
-	rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_draw(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DRAW, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002;
-	rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004;
-
-	radeon_state_pm4(rstate);
+	state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
+	state->flags |= R600_STATE_FLAG_DSA_FLUSH;
+	return state;
+		
 }
 
-static void r600_blit_state_vs_constant(struct r600_screen *rscreen, struct radeon_state *rstate,
-					unsigned id, float c0, float c1, float c2, float c3)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256] = fui(c0);
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256] = fui(c1);
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2);
-	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3);
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_rasterizer(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
-	rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
-	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
-	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004;
-	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_dsa(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	uint32_t db_render_override, db_shader_control;
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
-	rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
-
-	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
-		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
-
-	db_shader_control = S_02880C_DUAL_EXPORT_ENABLE(0) |
-		S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
-
-	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = db_render_override;
-	rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_blend(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_cb_cntl(struct r600_screen *rscreen, struct radeon_state *rstate)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
-	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
-	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0080;
-	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
-	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
-	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	rstate->states[R600_CB_CNTL__CB_SHADER_CONTROL] = 0x1;
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_cb_flush(struct r600_screen *rscreen, struct radeon_state *rstate, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_FLUSH, 0, 0);
-
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
-	rstate->nbo = 1;
-	radeon_state_pm4(rstate);
-}
-
-static void r600_blit_state_db_flush(struct r600_screen *rscreen, struct radeon_state *rstate, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB_FLUSH, 0, 0);
-
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->resource.bo);
-	rstate->nbo = 1;
-	radeon_state_pm4(rstate);
-}
-
-static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates)
+void r600_init_blit_functions(struct r600_context *rctx)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-
-	r600_blit_state_ps_shader(rscreen, &bstates->ps_shader);
-	r600_blit_state_vs_shader(rscreen, &bstates->vs_shader);
-	r600_blit_state_vgt(rscreen, &bstates->vgt);
-	r600_blit_state_draw(rscreen, &bstates->draw);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant0, 0, 1.0, 0.0, 0.0, 0.0);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant1, 1, 0.0, 1.0, 0.0, 0.0);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant2, 2, 0.0, 0.0, -0.00199900055, 0.0);
-	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant3, 3, 0.0, 0.0, -0.99900049, 1.0);
-	r600_blit_state_rasterizer(rscreen, &bstates->rasterizer);
-	r600_blit_state_dsa(rscreen, &bstates->dsa);
-	r600_blit_state_blend(rscreen, &bstates->blend);
-	r600_blit_state_cb_cntl(rscreen, &bstates->cb_cntl);
-	r600_blit_state_vs_resources(rscreen, bstates);
-	return 0;
-}
+	rctx->context.clear = r600_clear;
+	rctx->context.clear_render_target = r600_clear_render_target;
+	rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
+	rctx->context.resource_copy_region = r600_resource_copy_region;
 
-static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates)
-{
-	radeon_state_fini(&bstates->ps_shader);
-	radeon_state_fini(&bstates->vs_shader);
-	radeon_state_fini(&bstates->vs_resource0);
-	radeon_state_fini(&bstates->vs_resource1);
+	/* create a custom depth stencil for DB flush */
+	rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 }
 
-int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_draw draw;
-	struct r600_blit_states bstates;
+	struct r600_screen *rscreen = rctx->screen;
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+	struct pipe_surface *zsurf, *cbsurf;
 	enum radeon_family family;
-	int r;
+	int level = 0;
+	float depth = 1.0f;
 
-	r = r600_texture_scissor(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
-	r = r600_texture_cb(ctx, rtexture, 0, level);
-	if (r) {
-		return r;
-	}
-	r = r600_texture_db(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
-	r = r600_texture_viewport(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
+	zsurf = ctx->screen->get_tex_surface(ctx->screen, &texture->resource.base.b, 0, level, 0,
+					     PIPE_BIND_DEPTH_STENCIL);
 
-	r = r600_blit_states_init(ctx, &bstates);
-	if (r) {
-		return r;
-	}
+	cbsurf = ctx->screen->get_tex_surface(ctx->screen, texture->flushed_depth_texture, 0, level, 0,
+					      PIPE_BIND_RENDER_TARGET);
+
+	r600_blitter_save_states(ctx);
+	util_blitter_save_framebuffer(rctx->blitter, fb);
 
-	/* for some gpus we need special cases */
 	family = radeon_get_family(rscreen->rw);
-	/* according to R6xx_R7xx_3D.pdf section 6.3.1, these GPUs needs special handling */
 	if (family == CHIP_RV610 || family == CHIP_RV630 || family == CHIP_RV620 ||
-	    family == CHIP_RV635) {
-		bstates.dsa.states[R600_DSA__DB_DEPTH_CONTROL] = S_028800_Z_ENABLE(1) |
-			S_028800_STENCIL_ENABLE(1) | S_028800_ZFUNC(V_028800_STENCILFUNC_LEQUAL) |
-			S_028800_STENCILFUNC(V_028800_STENCILFUNC_ALWAYS) |
-			S_028800_STENCILZPASS(V_028800_STENCIL_KEEP) |
-			S_028800_STENCILZFAIL(V_028800_STENCIL_INCR);
-
-		bstates.dsa.states[R600_DSA__DB_STENCILREFMASK] = S_028430_STENCILWRITEMASK(0xff);
-	}
-	bstates.dsa.states[R600_DSA__DB_RENDER_CONTROL] = S_028D0C_DEPTH_COPY_ENABLE(1) |
-			S_028D0C_STENCIL_COPY_ENABLE(1) |
-			S_028D0C_COPY_CENTROID(1);
-
-	bstates.cb_cntl.states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000003;
-	r600_blit_state_cb_flush(rscreen, &bstates.cb_flush, rtexture, 0, 0);
-	r600_blit_state_db_flush(rscreen, &bstates.db_flush, rtexture, 0, 0);
-
-	/* force rebuild */
-	bstates.dsa.cpm4 = bstates.cb_cntl.cpm4 = 0;
-	if (radeon_state_pm4(&bstates.dsa)) {
-		goto out;
-	}
-	if (radeon_state_pm4(&bstates.cb_cntl)) {
-		goto out;
-	}
-
-	r = radeon_draw_init(&draw, rscreen->rw);
-	if (r) {
-		R600_ERR("failed creating draw for uncompressing textures\n");
-		goto out;
-	}
-
-	radeon_draw_bind(&draw, &bstates.vs_shader);
-	radeon_draw_bind(&draw, &bstates.ps_shader);
-	radeon_draw_bind(&draw, &bstates.rasterizer);
-	radeon_draw_bind(&draw, &bstates.dsa);
-	radeon_draw_bind(&draw, &bstates.blend);
-	radeon_draw_bind(&draw, &bstates.cb_cntl);
-	radeon_draw_bind(&draw, &rctx->config);
-	radeon_draw_bind(&draw, &bstates.vgt);
-	radeon_draw_bind(&draw, &bstates.draw);
-	radeon_draw_bind(&draw, &bstates.cb_flush);
-	radeon_draw_bind(&draw, &bstates.db_flush);
-	radeon_draw_bind(&draw, &bstates.vs_resource0);
-	radeon_draw_bind(&draw, &bstates.vs_resource1);
-	radeon_draw_bind(&draw, &bstates.vs_constant0);
-	radeon_draw_bind(&draw, &bstates.vs_constant1);
-	radeon_draw_bind(&draw, &bstates.vs_constant2);
-	radeon_draw_bind(&draw, &bstates.vs_constant3);
-	radeon_draw_bind(&draw, &rtexture->viewport[level]);
-	radeon_draw_bind(&draw, &rtexture->scissor[level]);
-	radeon_draw_bind(&draw, &rtexture->cb[0][level]);
-	radeon_draw_bind(&draw, &rtexture->db[level]);
-
-	/* suspend queries */
-	r600_queries_suspend(ctx);
-
-	/* schedule draw*/
-	r = radeon_ctx_set_draw(rctx->ctx, &draw);
-	if (r == -EBUSY) {
-		r600_flush(ctx, 0, NULL);
-		r = radeon_ctx_set_draw(rctx->ctx, &draw);
-	}
-	if (r) {
-		goto out;
-	}
+	    family == CHIP_RV635)
+		depth = 0.0f;
+	
+	util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, rctx->custom_dsa_flush, depth);
 
 	/* resume queries */
 	r600_queries_resume(ctx);
-
-out:
-	r600_blit_states_destroy(ctx, &bstates);
-	return r;
+	return 0;
 }
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 18ff7936899..b9abff9dc10 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -125,11 +125,12 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 	else
 		rctx->vtbl = &r600_hw_state_vtbl;
 
-	r600_init_blit_functions(rctx);
 	r600_init_query_functions(rctx);
 	r600_init_state_functions(rctx);
 	r600_init_context_resource_functions(rctx);
 
+	r600_init_blit_functions(rctx);
+
 	rctx->blitter = util_blitter_create(&rctx->context);
 	if (rctx->blitter == NULL) {
 		FREE(rctx);
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 3107f189c78..8778f23a819 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -98,6 +98,7 @@ enum pipe_state_type {
 };
 
 #define R600_MAX_RSTATE		16
+#define R600_STATE_FLAG_DSA_FLUSH 1
 
 struct r600_context_state {
 	union pipe_states		state;
@@ -107,6 +108,7 @@ struct r600_context_state {
 	struct r600_shader		shader;
 	struct radeon_ws_bo		*bo;
 	unsigned			nrstate;
+	unsigned			flags;
 };
 
 struct r600_vertex_element
@@ -189,21 +191,6 @@ struct r600_context_hw_state_vtbl {
 	int (*vs_shader)(struct r600_context *rctx, struct r600_context_state *rpshader,
 			 struct radeon_state *state);
 	void (*init_config)(struct r600_context *rctx);
-
-
-	void (*texture_state_viewport)(struct r600_screen *rscreen,
-				       struct r600_resource_texture *rtexture,
-				       unsigned level);
-	void (*texture_state_cb)(struct r600_screen *rscreen,
-				 struct r600_resource_texture *rtexture,
-				 unsigned cb,
-				 unsigned level);
-	void (*texture_state_db)(struct r600_screen *rscreen,
-				 struct r600_resource_texture *rtexture,
-				 unsigned level);
-	void (*texture_state_scissor)(struct r600_screen *rscreen,
-				 struct r600_resource_texture *rtexture,
-				 unsigned level);
 };
 extern struct r600_context_hw_state_vtbl r600_hw_state_vtbl;
 extern struct r600_context_hw_state_vtbl eg_hw_state_vtbl;
@@ -257,6 +244,7 @@ struct r600_context {
 	struct u_upload_mgr *upload_ib;
 	bool any_user_vbs;
 
+	void *custom_dsa_flush;
 };
 
 /* Convenience cast wrapper. */
diff --git a/src/gallium/drivers/r600/r600_hw_states.c b/src/gallium/drivers/r600/r600_hw_states.c
index 13b1124d90e..f3cb3b1ae0e 100644
--- a/src/gallium/drivers/r600/r600_hw_states.c
+++ b/src/gallium/drivers/r600/r600_hw_states.c
@@ -134,12 +134,14 @@ static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
 	format = r600_translate_colorformat(rtex->resource.base.b.format);
 	swap = r600_translate_colorswap(rtex->resource.base.b.format);
 
+
 	color_info = S_0280A0_FORMAT(format) |
 		S_0280A0_COMP_SWAP(swap) |
 		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_SOURCE_FORMAT(1) |
 		S_0280A0_NUMBER_TYPE(ntype);
 
+	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) 
+		color_info |= S_0280A0_SOURCE_FORMAT(1);
 	rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
 	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
@@ -386,14 +388,20 @@ static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 	struct r600_query *rquery = NULL;
 	boolean query_running;
 	int i;
+	bool flush_db = FALSE;
 
 	if (rctx->ps_shader == NULL) {
 		return;
 	}
+	if (rctx->dsa->flags & R600_STATE_FLAG_DSA_FLUSH)
+		flush_db = TRUE;
+	
 	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
-	db_shader_control = S_02880C_DUAL_EXPORT_ENABLE(1) |
-		S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+
+	if (!flush_db)
+		db_shader_control = S_02880C_DUAL_EXPORT_ENABLE(1);
 
 	rshader = &rctx->ps_shader->shader;
 	if (rshader->uses_kill)
@@ -441,8 +449,13 @@ static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 		alpha_ref = fui(state->alpha.ref_value);
 	}
 
-	db_render_control = S_028D0C_STENCIL_COMPRESS_DISABLE(1) |
-		S_028D0C_DEPTH_COMPRESS_DISABLE(1);
+	db_render_control = 0;
+
+	if (flush_db)
+		db_render_control = S_028D0C_DEPTH_COPY_ENABLE(1) |
+			S_028D0C_STENCIL_COPY_ENABLE(1) |
+			S_028D0C_COPY_CENTROID(1);
+
 	db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
 		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
 		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
@@ -545,7 +558,6 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
 	unsigned format;
 	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
-	int r;
 
 	rstate->cpm4 = 0;
 	swizzle[0] = view->swizzle_r;
@@ -566,17 +578,15 @@ static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
 	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
 	texture = (struct r600_resource_texture*)view->texture;
 	rbuffer = &texture->resource;
+
 	if (texture->depth) {
-		r = r600_texture_from_depth(ctx, texture, view->first_level);
-		if (r) {
-			return;
-		}
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], texture->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], texture->uncompressed);
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
+		r600_texture_depth_flush(ctx, view->texture);
+		rbuffer = &texture->flushed_depth_texture->resource;
 	}
+
+	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
+	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
+
 	rstate->nbo = 2;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
@@ -1077,164 +1087,6 @@ static int r600_vs_shader(struct r600_context *rctx, struct r600_context_state *
 	return radeon_state_pm4(state);
 }
 
-static void r600_texture_state_scissor(struct r600_screen *rscreen,
-					struct r600_resource_texture *rtexture,
-					unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->scissor[level];
-	enum radeon_family family;
-
-	family = radeon_get_family(rscreen->rw);
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-
-	if (family >= CHIP_RV770)
-		rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	struct radeon_state *rstate;
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-
-	rstate = &rtexture->cb[cb][level];
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
-	rbuffer = &rtexture->resource;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	ntype = 0;
-	desc = util_format_description(rbuffer->base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_0280A0_NUMBER_SRGB;
-	format = r600_translate_colorformat(rtexture->resource.base.b.format);
-	swap = r600_translate_colorswap(rtexture->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rtexture->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rtexture->uncompressed);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rtexture->uncompressed);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 3;
-		color_info = 0;
-	} else {
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[1], rbuffer->bo);
-		radeon_ws_bo_reference(rscreen->rw, &rstate->bo[2], rbuffer->bo);
-		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-		rstate->nbo = 3;
-		color_info = S_0280A0_SOURCE_FORMAT(1);
-	}
-	color_info |= S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
-						S_028060_SLICE_TILE_MAX(slice);
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->db[level];
-	struct r600_resource *rbuffer;
-	unsigned pitch, slice, format;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
-	rbuffer = &rtexture->resource;
-	rtexture->tiled = 1;
-	rtexture->array_mode = 2;
-	rtexture->tile_type = 1;
-	rtexture->depth = 1;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
-	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
-	format = r600_translate_dbformat(rbuffer->base.b.format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
-					S_028010_FORMAT(format);
-	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
-	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 1;
-
-	radeon_state_pm4(rstate);
-}
-
-static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct radeon_state *rstate = &rtexture->viewport[level];
-	float width, height;
-
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
-
-	width = rtexture->width[level] * 0.5;
-	height = rtexture->height[level] * 0.5;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(width);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(width);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(height);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(height);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(0.0);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(1.0);
-	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] =
-		S_028818_VPORT_X_SCALE_ENA(1) |
-		S_028818_VPORT_X_OFFSET_ENA(1) |
-		S_028818_VPORT_Y_SCALE_ENA(1) |
-		S_028818_VPORT_Y_OFFSET_ENA(1) |
-		S_028818_VPORT_Z_SCALE_ENA(1) |
-		S_028818_VPORT_Z_OFFSET_ENA(1) |
-		S_028818_VTX_W0_FMT(1);
-	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = fui(1);
-
-	radeon_state_pm4(rstate);
-}
-
 struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
 	.blend = r600_blend,
 	.ucp = r600_ucp,
@@ -1254,10 +1106,6 @@ struct r600_context_hw_state_vtbl r600_hw_state_vtbl = {
 	.vs_shader = r600_vs_shader,
 	.ps_shader = r600_ps_shader,
 	.init_config = r600_init_config,
-	.texture_state_viewport = r600_texture_state_viewport,
-	.texture_state_db = r600_texture_state_db,
-	.texture_state_cb = r600_texture_state_cb,
-	.texture_state_scissor = r600_texture_state_scissor,
 };
 
 void r600_set_constant_buffer_file(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 5d569106451..a24197c3c23 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -55,11 +55,7 @@ struct r600_resource_texture {
 	unsigned			tile_type;
 	unsigned			depth;
 	unsigned			dirty;
-	struct radeon_ws_bo		*uncompressed;
-	struct radeon_state		scissor[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		cb[8][PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		db[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		viewport[PIPE_MAX_TEXTURE_LEVELS];
+	struct r600_resource_texture    *flushed_depth_texture;
 };
 
 void r600_init_context_resource_functions(struct r600_context *r600);
@@ -106,4 +102,6 @@ static INLINE boolean r600_buffer_is_user_buffer(struct pipe_resource *buffer)
     return r600_buffer(buffer)->user_buffer ? TRUE : FALSE;
 }
 
+int r600_texture_depth_flush(struct pipe_context *ctx,
+			     struct pipe_resource *texture);
 #endif
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 502444f03ac..4105bb7cf61 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -77,14 +77,9 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 				struct pipe_transfer* transfer);
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 				 struct pipe_transfer* transfer);
-int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level);
-int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 
 /* r600_blit.c */
-int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
+int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 
 /* helpers */
 int r600_conv_pipe_format(unsigned pformat, unsigned *format);
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 37822903e82..b0d3b28c720 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -136,19 +136,6 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 	return &resource->base.b;
 }
 
-static void r600_texture_destroy_state(struct pipe_resource *ptexture)
-{
-	struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
-
-	for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
-		radeon_state_fini(&rtexture->scissor[i]);
-		radeon_state_fini(&rtexture->db[i]);
-		for (int j = 0; j < 8; j++) {
-			radeon_state_fini(&rtexture->cb[j][i]);
-		}
-	}
-}
-
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
@@ -156,13 +143,12 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	struct r600_resource *resource = &rtex->resource;
 	struct radeon *radeon = (struct radeon *)screen->winsys;
 
+	if (rtex->flushed_depth_texture)
+		pipe_resource_reference(&rtex->flushed_depth_texture, NULL);
+
 	if (resource->bo) {
 		radeon_ws_bo_reference(radeon, &resource->bo, NULL);
 	}
-	if (rtex->uncompressed) {
-		radeon_ws_bo_reference(radeon, &rtex->uncompressed, NULL);
-	}
-	r600_texture_destroy_state(ptex);
 	FREE(rtex);
 }
 
@@ -248,6 +234,39 @@ static unsigned int r600_texture_is_referenced(struct pipe_context *context,
 	return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 }
 
+int r600_texture_depth_flush(struct pipe_context *ctx,
+			     struct pipe_resource *texture)
+{
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+	struct pipe_resource resource;
+
+	if (rtex->flushed_depth_texture)
+		goto out;
+
+	resource.target = PIPE_TEXTURE_2D;
+	resource.format = texture->format;
+	resource.width0 = texture->width0;
+	resource.height0 = texture->height0;
+	resource.depth0 = 0;
+	resource.last_level = 0;
+	resource.nr_samples = 0;
+	resource.usage = PIPE_USAGE_DYNAMIC;
+	resource.bind = 0;
+	resource.flags = 0;
+
+	resource.bind |= PIPE_BIND_RENDER_TARGET;
+
+	rtex->flushed_depth_texture = ctx->screen->resource_create(ctx->screen, &resource);
+	if (rtex->flushed_depth_texture == NULL) {
+		R600_ERR("failed to create temporary texture to hold untiled copy\n");
+		return -ENOMEM;
+	}
+
+out:
+	r600_blit_uncompress_depth(ctx, rtex);
+	return 0;
+}
+
 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 						struct pipe_resource *texture,
 						struct pipe_subresource sr,
@@ -257,6 +276,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 	struct pipe_resource resource;
 	struct r600_transfer *trans;
+	int r;
 
 	trans = CALLOC_STRUCT(r600_transfer);
 	if (trans == NULL)
@@ -267,7 +287,15 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	trans->transfer.box = *box;
 	trans->transfer.stride = rtex->pitch[sr.level];
 	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
-	if (rtex->tiled && !rtex->depth) {
+	if (rtex->depth) {
+		r = r600_texture_depth_flush(ctx, texture);
+		if (r < 0) {
+			R600_ERR("failed to create temporary texture to hold untiled copy\n");
+			pipe_resource_reference(&trans->transfer.resource, NULL);
+			FREE(trans);
+			return NULL;
+		}
+	} else if (rtex->tiled) {
 		resource.target = PIPE_TEXTURE_2D;
 		resource.format = texture->format;
 		resource.width0 = box->width;
@@ -311,10 +339,17 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
 				   struct pipe_transfer *transfer)
 {
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
 
 	if (rtransfer->linear_texture) {
 		pipe_resource_reference(&rtransfer->linear_texture, NULL);
 	}
+	if (rtex->flushed_depth_texture) {
+		if (transfer->usage & PIPE_TRANSFER_WRITE) {
+			// TODO
+		}
+		pipe_resource_reference(&rtex->flushed_depth_texture, NULL);
+	}
 	pipe_resource_reference(&transfer->resource, NULL);
 	FREE(transfer);
 }
@@ -326,25 +361,19 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 	struct radeon_ws_bo *bo;
 	enum pipe_format format = transfer->resource->format;
 	struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
-	struct r600_resource_texture *rtex;
 	unsigned long offset = 0;
 	char *map;
-	int r;
 
 	if (rtransfer->linear_texture) {
 		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
-		rtex = (struct r600_resource_texture*)transfer->resource;
-		if (rtex->depth && radeon_get_family_class(radeon) != EVERGREEN) {
-			r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
-			if (r) {
-				return NULL;
-			}
-			r600_flush(ctx, 0, NULL);
-			bo = rtex->uncompressed;
-		} else {
+		struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
+
+		if (rtex->flushed_depth_texture)
+			bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
+		else
 			bo = ((struct r600_resource *)transfer->resource)->bo;
-		}
+
 		offset = rtransfer->offset +
 			transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
 			transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
@@ -362,15 +391,15 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 {
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 	struct radeon *radeon = (struct radeon *)ctx->screen->winsys;
-	struct r600_resource_texture *rtex;
 	struct radeon_ws_bo *bo;
 
 	if (rtransfer->linear_texture) {
 		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
-		rtex = (struct r600_resource_texture*)transfer->resource;
-		if (rtex->depth) {
-			bo = rtex->uncompressed;
+		struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
+
+		if (rtex->flushed_depth_texture) {
+			bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo;
 		} else {
 			bo = ((struct r600_resource *)transfer->resource)->bo;
 		}
@@ -644,74 +673,3 @@ out_unknown:
 //	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
 	return ~0;
 }
-
-int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	int r;
-
-	/* TODO possible dirty handling */
-
-	/* allocate uncompressed texture */
-	if (rtexture->uncompressed == NULL) {
-		rtexture->uncompressed = radeon_ws_bo(rscreen->rw, rtexture->size, 4096, 0);
-		if (rtexture->uncompressed == NULL) {
-			return -ENOMEM;
-		}
-	}
-
-	/* render a rectangle covering whole buffer to uncompress depth */
-	r = r600_blit_uncompress_depth(ctx, rtexture, level);
-	if (r) {
-		return r;
-	}
-
-	rtexture->dirty = 0;
-	return 0;
-}
-
-
-
-int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->scissor[level].cpm4) {
-		rctx->vtbl->texture_state_scissor(rscreen, rtexture, level);
-	}
-	return 0;
-}
-
-int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->cb[cb][level].cpm4) {
-		rctx->vtbl->texture_state_cb(rscreen, rtexture, cb, level);
-	}
-	return 0;
-}
-
-int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->db[level].cpm4) {
-		rctx->vtbl->texture_state_db(rscreen, rtexture, level);
-	}
-	return 0;
-}
-
-int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (!rtexture->viewport[level].cpm4) {
-		rctx->vtbl->texture_state_viewport(rscreen, rtexture, level);
-	}
-	return 0;
-}