r600g: adjust flush flags (v3)

1. flush SH with read caches
2. add flag for DB flushes
3. add flag for CB flushes

v2: flush all CBs, remove redundant emit_state variable.
v3: Marek: also set the new flags in r600_context_flush, the CP dma functions,
    and texture_barrier, and rename them

Signed-off-by: Marek Olšák <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>

6 files changed, 42 insertions, 7 deletions

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c
index 7cab8794486..3c669cfaa4e 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -125,6 +125,8 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
 	 * to resources which are bound right now. */
 	rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
 		       R600_CONTEXT_FLUSH_AND_INV |
+		       R600_CONTEXT_FLUSH_AND_INV_CB |
+		       R600_CONTEXT_FLUSH_AND_INV_DB |
 		       R600_CONTEXT_FLUSH_AND_INV_CB_META |
 		       R600_CONTEXT_FLUSH_AND_INV_DB_META |
 		       R600_CONTEXT_STREAMOUT_FLUSH |
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 48de6c5249d..4166b18e262 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1715,6 +1715,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 
 	if (rctx->framebuffer.state.nr_cbufs) {
 		rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+		rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB;
 
 		if (rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
 			rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
@@ -1722,6 +1723,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 	}
 	if (rctx->framebuffer.state.zsbuf) {
 		rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+		rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
 
 		rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
 		if (rtex->htile) {
diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c
index 944b666c2dd..120d0fd354a 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -185,7 +185,6 @@ void r600_flush_emit(struct r600_context *rctx)
 	struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
 	unsigned cp_coher_cntl = 0;
 	unsigned wait_until = 0;
-	unsigned emit_flush = 0;
 
 	if (!rctx->flags) {
 		return;
@@ -231,8 +230,32 @@ void r600_flush_emit(struct r600_context *rctx)
 	if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {
 		cp_coher_cntl |= S_0085F0_VC_ACTION_ENA(1) |
 				S_0085F0_TC_ACTION_ENA(1) |
+				S_0085F0_SH_ACTION_ENA(1) |
 				S_0085F0_FULL_CACHE_ENA(1);
-		emit_flush = 1;
+	}
+
+	if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
+		cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
+				S_0085F0_DB_DEST_BASE_ENA(1) |
+				S_0085F0_SMX_ACTION_ENA(1);
+	}
+
+	if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
+		cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
+				S_0085F0_CB0_DEST_BASE_ENA(1) |
+				S_0085F0_CB1_DEST_BASE_ENA(1) |
+				S_0085F0_CB2_DEST_BASE_ENA(1) |
+				S_0085F0_CB3_DEST_BASE_ENA(1) |
+				S_0085F0_CB4_DEST_BASE_ENA(1) |
+				S_0085F0_CB5_DEST_BASE_ENA(1) |
+				S_0085F0_CB6_DEST_BASE_ENA(1) |
+				S_0085F0_CB7_DEST_BASE_ENA(1) |
+				S_0085F0_SMX_ACTION_ENA(1);
+		if (rctx->chip_class >= EVERGREEN)
+			cp_coher_cntl |= S_0085F0_CB8_DEST_BASE_ENA(1) |
+					S_0085F0_CB9_DEST_BASE_ENA(1) |
+					S_0085F0_CB10_DEST_BASE_ENA(1) |
+					S_0085F0_CB11_DEST_BASE_ENA(1);
 	}
 
 	if (rctx->flags & R600_CONTEXT_STREAMOUT_FLUSH) {
@@ -241,10 +264,9 @@ void r600_flush_emit(struct r600_context *rctx)
 				S_0085F0_SO2_DEST_BASE_ENA(1) |
 				S_0085F0_SO3_DEST_BASE_ENA(1) |
 				S_0085F0_SMX_ACTION_ENA(1);
-		emit_flush = 1;
 	}
 
-	if (emit_flush) {
+	if (cp_coher_cntl) {
 		cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
 		cs->buf[cs->cdw++] = cp_coher_cntl;   /* CP_COHER_CNTL */
 		cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
@@ -289,6 +311,8 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 	 * this will also flush the framebuffer cache
 	 */
 	ctx->flags |= R600_CONTEXT_FLUSH_AND_INV |
+		      R600_CONTEXT_FLUSH_AND_INV_CB |
+		      R600_CONTEXT_FLUSH_AND_INV_DB |
 		      R600_CONTEXT_FLUSH_AND_INV_CB_META |
 		      R600_CONTEXT_FLUSH_AND_INV_DB_META |
 		      R600_CONTEXT_WAIT_3D_IDLE |
@@ -594,6 +618,8 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx,
 	 * to resources which are bound right now. */
 	rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
 		       R600_CONTEXT_FLUSH_AND_INV |
+		       R600_CONTEXT_FLUSH_AND_INV_CB |
+		       R600_CONTEXT_FLUSH_AND_INV_DB |
 		       R600_CONTEXT_FLUSH_AND_INV_CB_META |
 		       R600_CONTEXT_FLUSH_AND_INV_DB_META |
 		       R600_CONTEXT_STREAMOUT_FLUSH |
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 64a90c3b3e9..0a244a8aacc 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -72,6 +72,8 @@
 #define R600_CONTEXT_FLUSH_AND_INV_CB_META	(1 << 5)
 #define R600_CONTEXT_PS_PARTIAL_FLUSH		(1 << 6)
 #define R600_CONTEXT_FLUSH_AND_INV_DB_META      (1 << 7)
+#define R600_CONTEXT_FLUSH_AND_INV_DB		(1 << 8)
+#define R600_CONTEXT_FLUSH_AND_INV_CB		(1 << 9)
 
 #define R600_QUERY_DRAW_CALLS		(PIPE_QUERY_DRIVER_SPECIFIC + 0)
 #define R600_QUERY_REQUESTED_VRAM	(PIPE_QUERY_DRIVER_SPECIFIC + 1)
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 068d87126e5..759f71f97e7 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1553,6 +1553,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 
 	if (rctx->framebuffer.state.nr_cbufs) {
 		rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+		rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_CB;
 
 		if (rctx->chip_class >= R700 &&
 		    rctx->framebuffer.state.cbufs[0]->texture->nr_samples > 1) {
@@ -1561,6 +1562,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	}
 	if (rctx->framebuffer.state.zsbuf) {
 		rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
+		rctx->flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
 
 		rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture;
 		if (rctx->chip_class >= R700 && rtex->htile) {
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index b9a8f0bc09d..d05675eef5d 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -89,9 +89,10 @@ static void r600_texture_barrier(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 
-	rctx->flags |= R600_CONTEXT_WAIT_3D_IDLE;
-	rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
-	rctx->flags |= R600_CONTEXT_FLUSH_AND_INV;
+	rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
+		       R600_CONTEXT_FLUSH_AND_INV_CB |
+		       R600_CONTEXT_FLUSH_AND_INV |
+		       R600_CONTEXT_WAIT_3D_IDLE;
 }
 
 static unsigned r600_conv_pipe_prim(unsigned prim)