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authorConnor Abbott <[email protected]>2019-05-24 15:08:06 +0200
committerConnor Abbott <[email protected]>2019-06-04 15:15:46 +0200
commitd68218dbca9c41d94e1547e82b6930750d9edb66 (patch)
tree9eee49b2d99e325f2040572d12e4f244826b3a7c /src/gallium
parenta6e879984cb7a5c22f25da47b82ba23800af32b2 (diff)
radeonsi/nir: Fix type in bindless address computation
Bindless handles in GL are 64-bit. This fixes an assert failure in LLVM. Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_shader_nir.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 19ed71ae05d..72e6ffbac8a 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -1020,7 +1020,7 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
* 16-dword slots for now.
*/
dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
- LLVMConstInt(ctx->i32, 2, 0), "");
+ LLVMConstInt(ctx->i64, 2, 0), "");
return si_load_image_desc(ctx, list, dynamic_index, desc_type,
dcc_off, true);
@@ -1032,7 +1032,7 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
* to prevent incorrect code generation and hangs.
*/
dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
- LLVMConstInt(ctx->i32, 2, 0), "");
+ LLVMConstInt(ctx->i64, 2, 0), "");
list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
}