Merge remote-tracking branch 'origin/master' into pipe-video

Conflicts: src/gallium/drivers/r600/r600_pipe.c src/gallium/drivers/r600/r600_state_inlines.h
author: Christian König <[email protected]> 2011-07-11 10:48:59 +0200
committer: Christian König <[email protected]> 2011-07-11 10:48:59 +0200
commit: f919547f3785b1d8839b9fc5c00ac397e30896a1 (patch)
tree: 910cd4fd7ffcd2781a303bb79395a0ee3c044c7d /src/gallium
parent: cd4f18089e44872ce9e3c04ac5e808a7204ffc49 (diff)
parent: 12265d26ddc72f62de927ac24e12ab41fcd8d1c5 (diff)
60 files changed, 2300 insertions, 1797 deletions
diff --git a/src/gallium/auxiliary/draw/draw_llvm.c b/src/gallium/auxiliary/draw/draw_llvm.c
index f33c9078c9c..8bb87440497 100644
--- a/src/gallium/auxiliary/draw/draw_llvm.c
+++ b/src/gallium/auxiliary/draw/draw_llvm.c
@@ -1235,7 +1235,8 @@ draw_llvm_generate(struct draw_llvm *llvm, struct draw_llvm_variant *variant)
       draw_llvm_variant_key_samplers(&variant->key),
       context_ptr);
 
-   fetch_max = LLVMBuildSub(builder, count,
+   /* fetch_max = start + count - 1 */
+   fetch_max = LLVMBuildSub(builder, end,
                             lp_build_const_int32(gallivm, 1),
                             "fetch_max");
 
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
index 01e660ef7d9..29dfb868d95 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
@@ -207,21 +207,13 @@ lp_disassemble(const void* func)
    }
 
    raw_debug_ostream Out;
-#if HAVE_LLVM >= 0x0300
-   TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), "");
-#else
-   TargetMachine *TM = T->createTargetMachine(Triple, "");
-#endif
 
 #if HAVE_LLVM >= 0x0300
    unsigned int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
 #else
    int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
 #endif
-#if HAVE_LLVM >= 0x0300
-   OwningPtr<MCInstPrinter> Printer(
-         T->createMCInstPrinter(*TM, AsmPrinterVariant, *AsmInfo));
-#elif HAVE_LLVM >= 0x0208
+#if HAVE_LLVM >= 0x0208
    OwningPtr<MCInstPrinter> Printer(
          T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo));
 #else
@@ -233,6 +225,12 @@ lp_disassemble(const void* func)
       return;
    }
 
+#if HAVE_LLVM >= 0x0300
+   TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), "");
+#else
+   TargetMachine *TM = T->createTargetMachine(Triple, "");
+#endif
+
    const TargetInstrInfo *TII = TM->getInstrInfo();
 
    /*
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index 9cf74a838fe..712e8aca794 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -1839,6 +1839,17 @@ exec_tex(struct tgsi_exec_machine *mach,
       assert(0);
    }
 
+#if 0
+   debug_printf("fetch r: %g %g %g %g\n",
+         r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
+   debug_printf("fetch g: %g %g %g %g\n",
+         r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
+   debug_printf("fetch b: %g %g %g %g\n",
+         r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
+   debug_printf("fetch a: %g %g %g %g\n",
+         r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
+#endif
+
    for (chan = 0; chan < NUM_CHANNELS; chan++) {
       if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
          store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
diff --git a/src/gallium/auxiliary/util/u_pack_color.h b/src/gallium/auxiliary/util/u_pack_color.h
index 5378f2d782f..9391f1b80e0 100644
--- a/src/gallium/auxiliary/util/u_pack_color.h
+++ b/src/gallium/auxiliary/util/u_pack_color.h
@@ -458,6 +458,19 @@ util_pack_mask_z(enum pipe_format format, uint32_t z)
    }
 }
 
+
+static INLINE uint64_t
+util_pack64_mask_z(enum pipe_format format, uint32_t z)
+{
+   switch (format) {
+   case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+      return z;
+   default:
+      return util_pack_mask_z(format, z);
+   }
+}
+
+
 static INLINE uint32_t
 util_pack_mask_z_stencil(enum pipe_format format, uint32_t z, uint8_t s)
 {
@@ -481,6 +494,21 @@ util_pack_mask_z_stencil(enum pipe_format format, uint32_t z, uint8_t s)
 }
 
 
+static INLINE uint64_t
+util_pack64_mask_z_stencil(enum pipe_format format, uint32_t z, uint8_t s)
+{
+   uint64_t packed;
+
+   switch (format) {
+   case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+      packed = util_pack64_mask_z(format, z);
+      packed |= (uint64_t)s << 32ull;
+      return packed;
+   default:
+      return util_pack_mask_z_stencil(format, z, s);
+   }
+}
+
 
 /**
  * Note: it's assumed that z is in [0,1]
@@ -525,6 +553,24 @@ util_pack_z(enum pipe_format format, double z)
       return 0;
    }
 }
+
+
+static INLINE uint64_t
+util_pack64_z(enum pipe_format format, double z)
+{
+   union fi fui;
+
+   if (z == 0)
+      return 0;
+
+   switch (format) {
+   case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+      fui.f = (float)z;
+      return fui.ui;
+   default:
+      return util_pack_z(format, z);
+   }
+}
  
 
 /**
@@ -554,6 +600,24 @@ util_pack_z_stencil(enum pipe_format format, double z, uint8_t s)
 }
 
 
+static INLINE uint64_t
+util_pack64_z_stencil(enum pipe_format format, double z, uint8_t s)
+{
+   uint64_t packed;
+
+   switch (format) {
+   case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+      packed = util_pack64_z(format, z);
+      packed |= (uint64_t)s << 32ull;
+      break;
+   default:
+      return util_pack_z_stencil(format, z, s);
+   }
+
+   return packed;
+}
+
+
 /**
  * Pack 4 ubytes into a 4-byte word
  */
diff --git a/src/gallium/auxiliary/util/u_surface.c b/src/gallium/auxiliary/util/u_surface.c
index 4c5cc4da182..8e123867da6 100644
--- a/src/gallium/auxiliary/util/u_surface.c
+++ b/src/gallium/auxiliary/util/u_surface.c
@@ -358,8 +358,41 @@ util_clear_depth_stencil(struct pipe_context *pipe,
                dst_map += dst_stride;
             }
          }
-        break;
+         break;
       case 8:
+      {
+         uint64_t zstencil = util_pack64_z_stencil(dst->texture->format,
+                                                   depth, stencil);
+
+         assert(dst->format == PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED);
+
+         if (!need_rmw) {
+            for (i = 0; i < height; i++) {
+               uint64_t *row = (uint64_t *)dst_map;
+               for (j = 0; j < width; j++)
+                  *row++ = zstencil;
+               dst_map += dst_stride;
+            }
+         }
+         else {
+            uint64_t src_mask;
+
+            if (clear_flags & PIPE_CLEAR_DEPTH)
+               src_mask = 0x00000000ffffffffull;
+            else
+               src_mask = 0x000000ff00000000ull;
+
+            for (i = 0; i < height; i++) {
+               uint64_t *row = (uint64_t *)dst_map;
+               for (j = 0; j < width; j++) {
+                  uint64_t tmp = *row & ~src_mask;
+                  *row++ = tmp | (zstencil & src_mask);
+               }
+               dst_map += dst_stride;
+            }
+         }
+         break;
+      }
       default:
          assert(0);
          break;
diff --git a/src/gallium/auxiliary/util/u_tile.c b/src/gallium/auxiliary/util/u_tile.c
index e3c7085ba92..23f12e5f464 100644
--- a/src/gallium/auxiliary/util/u_tile.c
+++ b/src/gallium/auxiliary/util/u_tile.c
@@ -318,6 +318,32 @@ z32f_get_tile_rgba(const float *src,
    }
 }
 
+/*** PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED ***/
+
+/**
+ * Return each Z value as four floats in [0,1].
+ */
+static void
+z32f_x24s8_get_tile_rgba(const float *src,
+                         unsigned w, unsigned h,
+                         float *p,
+                         unsigned dst_stride)
+{
+   unsigned i, j;
+
+   for (i = 0; i < h; i++) {
+      float *pRow = p;
+      for (j = 0; j < w; j++, pRow += 4) {
+         pRow[0] =
+         pRow[1] =
+         pRow[2] =
+         pRow[3] = *src;
+         src += 2;
+      }
+      p += dst_stride;
+   }
+}
+
 
 void
 pipe_tile_raw_to_rgba(enum pipe_format format,
@@ -352,6 +378,9 @@ pipe_tile_raw_to_rgba(enum pipe_format format,
    case PIPE_FORMAT_Z32_FLOAT:
       z32f_get_tile_rgba((float *) src, w, h, dst, dst_stride);
       break;
+   case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+      z32f_x24s8_get_tile_rgba((float *) src, w, h, dst, dst_stride);
+      break;
    default:
       util_format_read_4f(format,
                           dst, dst_stride * sizeof(float),
@@ -445,6 +474,12 @@ pipe_put_tile_rgba_format(struct pipe_context *pipe,
    case PIPE_FORMAT_X8Z24_UNORM:
       /*z24s8_put_tile_rgba((unsigned *) packed, w, h, p, src_stride);*/
       break;
+   case PIPE_FORMAT_Z32_FLOAT:
+      /*z32f_put_tile_rgba((unsigned *) packed, w, h, p, src_stride);*/
+      break;
+   case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+      /*z32f_s8x24_put_tile_rgba((unsigned *) packed, w, h, p, src_stride);*/
+      break;
    default:
       util_format_write_4f(format,
                            p, src_stride * sizeof(float),
diff --git a/src/gallium/drivers/i915/Makefile b/src/gallium/drivers/i915/Makefile
index 778124728bb..36197fbc93b 100644
--- a/src/gallium/drivers/i915/Makefile
+++ b/src/gallium/drivers/i915/Makefile
@@ -27,6 +27,7 @@ C_SOURCES = \
 	i915_resource_buffer.c \
 	i915_fpc_emit.c \
 	i915_fpc_translate.c \
+	i915_fpc_optimize.c \
 	i915_surface.c 
 
 include ../../Makefile.template
diff --git a/src/gallium/drivers/i915/SConscript b/src/gallium/drivers/i915/SConscript
index 98370601b7f..76f597001fe 100644
--- a/src/gallium/drivers/i915/SConscript
+++ b/src/gallium/drivers/i915/SConscript
@@ -14,6 +14,7 @@ i915 = env.ConvenienceLibrary(
 		'i915_flush.c',
 		'i915_fpc_emit.c',
 		'i915_fpc_translate.c',
+		'i915_fpc_optimize.c',
 		'i915_prim_emit.c',
 		'i915_prim_vbuf.c',
 		'i915_query.c',
diff --git a/src/gallium/drivers/i915/i915_batch.h b/src/gallium/drivers/i915/i915_batch.h
index ce2691b2fd7..a1f8bcae802 100644
--- a/src/gallium/drivers/i915/i915_batch.h
+++ b/src/gallium/drivers/i915/i915_batch.h
@@ -29,6 +29,7 @@
 #define I915_BATCH_H
 
 #include "i915_batchbuffer.h"
+#include "i915_context.h"
 
 
 #define BEGIN_BATCH(dwords) \
@@ -49,11 +50,26 @@
 #define FLUSH_BATCH(fence) \
    i915_flush(i915, fence)
 
-
 /************************************************************************
  * i915_flush.c
  */
 void i915_flush(struct i915_context *i915, struct pipe_fence_handle **fence);
 
+/*
+ * Flush if the current color buf is idle and we have more than 256 vertices
+ * queued, or if the current color buf is busy and we have more than 4096
+ * vertices queued.
+ */
+static INLINE void i915_flush_heuristically(struct i915_context* i915,
+                                            int num_vertex)
+{
+   struct i915_winsys *iws = i915->iws;
+   i915->vertices_since_last_flush += num_vertex;
+   if ( i915->vertices_since_last_flush > 4096
+      || ( i915->vertices_since_last_flush > 256 &&
+           !iws->buffer_is_busy(iws, i915->current.cbuf_bo)) )
+      FLUSH_BATCH(NULL);
+}
+
 
 #endif
diff --git a/src/gallium/drivers/i915/i915_clear.c b/src/gallium/drivers/i915/i915_clear.c
index fcb208d6dae..e1d6a749cdc 100644
--- a/src/gallium/drivers/i915/i915_clear.c
+++ b/src/gallium/drivers/i915/i915_clear.c
@@ -120,6 +120,11 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers, const float *rgba,
    OUT_BATCH_F(desty + height);
    OUT_BATCH_F(destx);
    OUT_BATCH_F(desty);
+
+   /* Flush after clear, its expected to be a costly operation.
+    * This is not required, just a heuristic
+    */
+   FLUSH_BATCH(NULL);
 }
 
 /**
diff --git a/src/gallium/drivers/i915/i915_context.h b/src/gallium/drivers/i915/i915_context.h
index c964208fedd..84862351ffe 100644
--- a/src/gallium/drivers/i915/i915_context.h
+++ b/src/gallium/drivers/i915/i915_context.h
@@ -264,6 +264,8 @@ struct i915_context {
    struct util_slab_mempool transfer_pool;
    struct util_slab_mempool texture_transfer_pool;
 
+   int vertices_since_last_flush;
+
    /** blitter/hw-clear */
    struct blitter_context* blitter;
 
diff --git a/src/gallium/drivers/i915/i915_flush.c b/src/gallium/drivers/i915/i915_flush.c
index b4e81147c4f..6d76afa9dbc 100644
--- a/src/gallium/drivers/i915/i915_flush.c
+++ b/src/gallium/drivers/i915/i915_flush.c
@@ -77,4 +77,5 @@ void i915_flush(struct i915_context *i915, struct pipe_fence_handle **fence)
    i915->static_dirty = ~0;
    /* kernel emits flushes in between batchbuffers */
    i915->flush_dirty = 0;
+   i915->vertices_since_last_flush = 0;
 }
diff --git a/src/gallium/drivers/i915/i915_fpc.h b/src/gallium/drivers/i915/i915_fpc.h
index 509395cf1f5..b760bc461a1 100644
--- a/src/gallium/drivers/i915/i915_fpc.h
+++ b/src/gallium/drivers/i915/i915_fpc.h
@@ -33,7 +33,9 @@
 #include "i915_context.h"
 #include "i915_reg.h"
 
+#include "pipe/p_shader_tokens.h"
 
+#include "tgsi/tgsi_parse.h"
 
 #define I915_PROGRAM_SIZE 192
 
@@ -207,4 +209,90 @@ extern void
 i915_program_error(struct i915_fp_compile *p, const char *msg, ...);
 
 
+/*======================================================================
+ * i915_fpc_optimize.c
+ */
+
+
+struct i915_src_register
+{
+   unsigned File        : 4;  /* TGSI_FILE_ */
+   unsigned Indirect    : 1;  /* BOOL */
+   unsigned Dimension   : 1;  /* BOOL */
+   int      Index       : 16; /* SINT */
+   unsigned SwizzleX    : 3;  /* TGSI_SWIZZLE_ */
+   unsigned SwizzleY    : 3;  /* TGSI_SWIZZLE_ */
+   unsigned SwizzleZ    : 3;  /* TGSI_SWIZZLE_ */
+   unsigned SwizzleW    : 3;  /* TGSI_SWIZZLE_ */
+   unsigned Absolute    : 1;    /* BOOL */
+   unsigned Negate      : 1;    /* BOOL */
+};
+
+/* Additional swizzle supported in i915 */
+#define TGSI_SWIZZLE_ZERO 4
+#define TGSI_SWIZZLE_ONE 5
+
+struct i915_dst_register
+{
+   unsigned File        : 4;  /* TGSI_FILE_ */
+   unsigned WriteMask   : 4;  /* TGSI_WRITEMASK_ */
+   unsigned Indirect    : 1;  /* BOOL */
+   unsigned Dimension   : 1;  /* BOOL */
+   int      Index       : 16; /* SINT */
+   unsigned Padding     : 6;
+};
+
+
+struct i915_full_dst_register
+{
+   struct i915_dst_register               Register;
+/*
+   struct tgsi_src_register               Indirect;
+   struct tgsi_dimension                  Dimension;
+   struct tgsi_src_register               DimIndirect;
+*/
+};
+
+struct i915_full_src_register
+{
+   struct i915_src_register         Register;
+/*
+   struct tgsi_src_register         Indirect;
+   struct tgsi_dimension            Dimension;
+   struct tgsi_src_register         DimIndirect;
+*/
+};
+
+struct i915_full_instruction
+{
+   struct tgsi_instruction             Instruction;
+/*
+   struct tgsi_instruction_predicate   Predicate;
+   struct tgsi_instruction_label       Label;
+*/
+   struct tgsi_instruction_texture     Texture;
+   struct i915_full_dst_register       Dst[1];
+   struct i915_full_src_register       Src[3];
+};
+
+
+union i915_full_token
+{
+   struct tgsi_token             Token;
+   struct tgsi_full_declaration  FullDeclaration;
+   struct tgsi_full_immediate    FullImmediate;
+   struct i915_full_instruction  FullInstruction;
+   struct tgsi_full_property     FullProperty;
+};
+
+struct i915_token_list
+{
+   union i915_full_token*     Tokens;
+   unsigned                   NumTokens;
+};
+
+extern struct i915_token_list* i915_optimize(const struct tgsi_token *tokens);
+
+extern void i915_optimize_free(struct i915_token_list* tokens);
+
 #endif
diff --git a/src/gallium/drivers/i915/i915_fpc_emit.c b/src/gallium/drivers/i915/i915_fpc_emit.c
index d28595e0fd3..c4a42df7882 100644
--- a/src/gallium/drivers/i915/i915_fpc_emit.c
+++ b/src/gallium/drivers/i915/i915_fpc_emit.c
@@ -369,7 +369,6 @@ i915_emit_const4f(struct i915_fp_compile * p,
 
    // XXX emit swizzle here for 0, 1, -1 and any combination thereof
    // we can use swizzle + neg for that
-   printf("const %f %f %f %f\n",c0,c1,c2,c3);
    for (reg = 0; reg < I915_MAX_CONSTANT; reg++) {
       if (ifs->constant_flags[reg] == 0xf &&
           ifs->constants[reg][0] == c0 &&
diff --git a/src/gallium/drivers/i915/i915_fpc_optimize.c b/src/gallium/drivers/i915/i915_fpc_optimize.c
new file mode 100644
index 00000000000..2b739e9ccb8
--- /dev/null
+++ b/src/gallium/drivers/i915/i915_fpc_optimize.c
@@ -0,0 +1,259 @@
+/**************************************************************************
+ * 
+ * Copyright 2011 The Chromium OS authors.
+ * All Rights Reserved.
+ * 
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL GOOGLE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * 
+ **************************************************************************/
+
+#include "i915_reg.h"
+#include "i915_context.h"
+#include "i915_fpc.h"
+
+#include "pipe/p_shader_tokens.h"
+#include "util/u_math.h"
+#include "util/u_memory.h"
+#include "util/u_string.h"
+#include "tgsi/tgsi_parse.h"
+#include "tgsi/tgsi_dump.h"
+
+static boolean same_dst_reg(struct i915_full_dst_register* d1, struct i915_full_dst_register* d2)
+{
+   return (d1->Register.File == d2->Register.File &&
+           d1->Register.Indirect == d2->Register.Indirect &&
+           d1->Register.Dimension == d2->Register.Dimension &&
+           d1->Register.Index == d2->Register.Index);
+}
+
+static boolean same_src_reg(struct i915_full_src_register* d1, struct i915_full_src_register* d2)
+{
+   return (d1->Register.File == d2->Register.File &&
+           d1->Register.Indirect == d2->Register.Indirect &&
+           d1->Register.Dimension == d2->Register.Dimension &&
+           d1->Register.Index == d2->Register.Index &&
+           d1->Register.Absolute == d2->Register.Absolute &&
+           d1->Register.Negate == d2->Register.Negate);
+}
+
+static boolean is_unswizzled(struct i915_full_src_register* r,
+                             unsigned write_mask)
+{
+   if ( write_mask & TGSI_WRITEMASK_X && r->Register.SwizzleX != TGSI_SWIZZLE_X)
+      return FALSE;
+   if ( write_mask & TGSI_WRITEMASK_Y && r->Register.SwizzleY != TGSI_SWIZZLE_Y)
+      return FALSE;
+   if ( write_mask & TGSI_WRITEMASK_Z && r->Register.SwizzleZ != TGSI_SWIZZLE_Z)
+      return FALSE;
+   if ( write_mask & TGSI_WRITEMASK_W && r->Register.SwizzleW != TGSI_SWIZZLE_W)
+      return FALSE;
+   return TRUE;
+}
+
+static boolean op_commutes(unsigned opcode)
+{
+   if (opcode == TGSI_OPCODE_ADD) return TRUE;
+   if (opcode == TGSI_OPCODE_MUL) return TRUE;
+   return FALSE;
+}
+
+static unsigned op_neutral_element(unsigned opcode)
+{
+   if (opcode == TGSI_OPCODE_ADD)
+      return TGSI_SWIZZLE_ZERO;
+   if (opcode == TGSI_OPCODE_MUL)
+      return TGSI_SWIZZLE_ONE;
+
+   debug_printf("Unknown opcode %d\n",opcode);
+   return TGSI_SWIZZLE_ZERO;
+}
+
+/*
+ * Sets the swizzle to the neutral element for the operation for the bits
+ * of writemask which are set, swizzle to identity otherwise.
+ */
+static void set_neutral_element_swizzle(struct i915_full_src_register* r,
+                                        unsigned write_mask,
+                                        unsigned neutral)
+{
+   if ( write_mask & TGSI_WRITEMASK_X )
+      r->Register.SwizzleX = neutral;
+   else
+      r->Register.SwizzleX = TGSI_SWIZZLE_X;
+
+   if ( write_mask & TGSI_WRITEMASK_Y )
+      r->Register.SwizzleY = neutral;
+   else
+      r->Register.SwizzleY = TGSI_SWIZZLE_Y;
+
+   if ( write_mask & TGSI_WRITEMASK_Z )
+      r->Register.SwizzleZ = neutral;
+   else
+      r->Register.SwizzleZ = TGSI_SWIZZLE_Z;
+
+   if ( write_mask & TGSI_WRITEMASK_W )
+      r->Register.SwizzleW = neutral;
+   else
+      r->Register.SwizzleW = TGSI_SWIZZLE_W;
+}
+
+/*
+ * Optimize away things like:
+ *    MUL OUT[0].xyz, TEMP[1], TEMP[2]
+ *    MOV OUT[0].w, TEMP[2]
+ * into: 
+ *    MUL OUT[0].xyzw, TEMP[1].xyz1, TEMP[2]
+ * This is useful for optimizing texenv.
+ */
+static void i915_fpc_optimize_mov_after_alu(union i915_full_token* current, union i915_full_token* next)
+{
+   if ( current->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
+        next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
+        op_commutes(current->FullInstruction.Instruction.Opcode) &&
+        current->FullInstruction.Instruction.Saturate == next->FullInstruction.Instruction.Saturate &&
+        next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
+        same_dst_reg(&next->FullInstruction.Dst[0], &next->FullInstruction.Dst[0]) &&
+        same_src_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Src[1]) &&
+        is_unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &&
+        is_unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) &&
+        is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) )
+   {
+      next->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
+
+      set_neutral_element_swizzle(&current->FullInstruction.Src[1], 0, 0);
+      set_neutral_element_swizzle(&current->FullInstruction.Src[0],
+                                  next->FullInstruction.Dst[0].Register.WriteMask,
+                                  op_neutral_element(current->FullInstruction.Instruction.Opcode));
+
+      current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.WriteMask |
+                                                           next->FullInstruction.Dst[0].Register.WriteMask;
+      return;
+   }
+
+   if ( current->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
+        next->Token.Type == TGSI_TOKEN_TYPE_INSTRUCTION  &&
+        op_commutes(current->FullInstruction.Instruction.Opcode) &&
+        current->FullInstruction.Instruction.Saturate == next->FullInstruction.Instruction.Saturate &&
+        next->FullInstruction.Instruction.Opcode == TGSI_OPCODE_MOV &&
+        same_dst_reg(&next->FullInstruction.Dst[0], &next->FullInstruction.Dst[0]) &&
+        same_src_reg(&next->FullInstruction.Src[0], &current->FullInstruction.Src[0]) &&
+        is_unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) &&
+        is_unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) &&
+        is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) )
+   {
+      next->FullInstruction.Instruction.Opcode = TGSI_OPCODE_NOP;
+
+      set_neutral_element_swizzle(&current->FullInstruction.Src[0], 0, 0);
+      set_neutral_element_swizzle(&current->FullInstruction.Src[1],
+                                  next->FullInstruction.Dst[0].Register.WriteMask,
+                                  op_neutral_element(current->FullInstruction.Instruction.Opcode));
+
+      current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.WriteMask |
+                                                           next->FullInstruction.Dst[0].Register.WriteMask;
+      return;
+   }
+}
+
+static void copy_src_reg(struct i915_src_register* o, const struct tgsi_src_register* i)
+{
+   o->File      = i->File;
+   o->Indirect  = i->Indirect;
+   o->Dimension = i->Dimension;
+   o->Index     = i->Index;
+   o->SwizzleX  = i->SwizzleX;
+   o->SwizzleY  = i->SwizzleY;
+   o->SwizzleZ  = i->SwizzleZ;
+   o->SwizzleW  = i->SwizzleW;
+   o->Absolute  = i->Absolute;
+   o->Negate    = i->Negate;
+}
+
+static void copy_dst_reg(struct i915_dst_register* o, const struct tgsi_dst_register* i)
+{
+   o->File      = i->File;
+   o->WriteMask = i->WriteMask;
+   o->Indirect  = i->Indirect;
+   o->Dimension = i->Dimension;
+   o->Index     = i->Index;
+}
+
+static void copy_instruction(struct i915_full_instruction* o, const struct tgsi_full_instruction* i)
+{
+   memcpy(&o->Instruction, &i->Instruction, sizeof(o->Instruction));
+   memcpy(&o->Texture, &i->Texture, sizeof(o->Texture));
+
+   copy_dst_reg(&o->Dst[0].Register, &i->Dst[0].Register);
+
+   copy_src_reg(&o->Src[0].Register, &i->Src[0].Register);
+   copy_src_reg(&o->Src[1].Register, &i->Src[1].Register);
+   copy_src_reg(&o->Src[2].Register, &i->Src[2].Register);
+}
+
+static void copy_token(union i915_full_token* o, union tgsi_full_token* i)
+{
+   if (i->Token.Type != TGSI_TOKEN_TYPE_INSTRUCTION)
+      memcpy(o, i, sizeof(*o));
+   else
+      copy_instruction(&o->FullInstruction, &i->FullInstruction);
+
+}
+
+struct i915_token_list* i915_optimize(const struct tgsi_token *tokens)
+{
+   struct i915_token_list *out_tokens = MALLOC(sizeof(struct i915_token_list));
+   struct tgsi_parse_context parse;
+   int i = 0;
+
+   out_tokens->NumTokens = 0;
+
+   /* Count the tokens */
+   tgsi_parse_init( &parse, tokens );
+   while( !tgsi_parse_end_of_tokens( &parse ) ) {
+      tgsi_parse_token( &parse );
+      out_tokens->NumTokens++;
+   }
+   tgsi_parse_free (&parse);
+
+   /* Allocate our tokens */
+   out_tokens->Tokens = MALLOC(sizeof(union i915_full_token) * out_tokens->NumTokens);
+
+   tgsi_parse_init( &parse, tokens );
+   while( !tgsi_parse_end_of_tokens( &parse ) ) {
+      tgsi_parse_token( &parse );
+      copy_token(&out_tokens->Tokens[i] , &parse.FullToken);
+
+      if (i > 0)
+         i915_fpc_optimize_mov_after_alu(&out_tokens->Tokens[i-1], &out_tokens->Tokens[i]);
+
+      i++;
+   }
+   tgsi_parse_free (&parse);
+
+   return out_tokens;
+}
+
+void i915_optimize_free(struct i915_token_list* tokens)
+{
+   free(tokens->Tokens);
+   free(tokens);
+}
+
+
diff --git a/src/gallium/drivers/i915/i915_fpc_translate.c b/src/gallium/drivers/i915/i915_fpc_translate.c
index 0cbd4f2d748..e19d9be04de 100644
--- a/src/gallium/drivers/i915/i915_fpc_translate.c
+++ b/src/gallium/drivers/i915/i915_fpc_translate.c
@@ -172,7 +172,7 @@ static uint get_mapping(struct i915_fragment_shader* fs, int unit)
  */
 static uint
 src_vector(struct i915_fp_compile *p,
-           const struct tgsi_full_src_register *source,
+           const struct i915_full_src_register *source,
            struct i915_fragment_shader* fs)
 {
    uint index = source->Register.Index;
@@ -287,7 +287,7 @@ src_vector(struct i915_fp_compile *p,
  */
 static uint
 get_result_vector(struct i915_fp_compile *p,
-                  const struct tgsi_full_dst_register *dest)
+                  const struct i915_full_dst_register *dest)
 {
    switch (dest->Register.File) {
    case TGSI_FILE_OUTPUT:
@@ -316,7 +316,7 @@ get_result_vector(struct i915_fp_compile *p,
  * Compute flags for saturation and writemask.
  */
 static uint
-get_result_flags(const struct tgsi_full_instruction *inst)
+get_result_flags(const struct i915_full_instruction *inst)
 {
    const uint writeMask
       = inst->Dst[0].Register.WriteMask;
@@ -378,7 +378,7 @@ translate_tex_src_target(struct i915_fp_compile *p, uint tex)
  */
 static void
 emit_tex(struct i915_fp_compile *p,
-         const struct tgsi_full_instruction *inst,
+         const struct i915_full_instruction *inst,
          uint opcode,
          struct i915_fragment_shader* fs)
 {
@@ -404,7 +404,7 @@ emit_tex(struct i915_fp_compile *p,
  */
 static void
 emit_simple_arith(struct i915_fp_compile *p,
-                  const struct tgsi_full_instruction *inst,
+                  const struct i915_full_instruction *inst,
                   uint opcode, uint numArgs,
                   struct i915_fragment_shader* fs)
 {
@@ -429,11 +429,11 @@ emit_simple_arith(struct i915_fp_compile *p,
 /** As above, but swap the first two src regs */
 static void
 emit_simple_arith_swap2(struct i915_fp_compile *p,
-                        const struct tgsi_full_instruction *inst,
+                        const struct i915_full_instruction *inst,
                         uint opcode, uint numArgs,
                         struct i915_fragment_shader* fs)
 {
-   struct tgsi_full_instruction inst2;
+   struct i915_full_instruction inst2;
 
    assert(numArgs == 2);
 
@@ -450,13 +450,14 @@ emit_simple_arith_swap2(struct i915_fp_compile *p,
  *
  * Possible concerns:
  *
+ * DDX, DDY -- return 0
  * SIN, COS -- could use another taylor step?
  * LIT      -- results seem a little different to sw mesa
  * LOG      -- different to mesa on negative numbers, but this is conformant.
  */ 
 static void
 i915_translate_instruction(struct i915_fp_compile *p,
-                           const struct tgsi_full_instruction *inst,
+                           const struct i915_full_instruction *inst,
                            struct i915_fragment_shader *fs)
 {
    uint writemask;
@@ -727,6 +728,9 @@ i915_translate_instruction(struct i915_fp_compile *p,
       emit_simple_arith(p, inst, A0_MUL, 2, fs);
       break;
 
+   case TGSI_OPCODE_NOP:
+      break;
+
    case TGSI_OPCODE_POW:
       src0 = src_vector(p, &inst->Src[0], fs);
       src1 = src_vector(p, &inst->Src[1], fs);
@@ -1043,107 +1047,107 @@ i915_translate_instruction(struct i915_fp_compile *p,
 }
 
 
-/**
- * Translate TGSI fragment shader into i915 hardware instructions.
- * \param p  the translation state
- * \param tokens  the TGSI token array
- */
-static void
-i915_translate_instructions(struct i915_fp_compile *p,
-                            const struct tgsi_token *tokens,
-                            struct i915_fragment_shader *fs)
+static void i915_translate_token(struct i915_fp_compile *p,
+                                 const union i915_full_token* token,
+                                 struct i915_fragment_shader *fs)
 {
    struct i915_fragment_shader *ifs = p->shader;
-   struct tgsi_parse_context parse;
-
-   tgsi_parse_init( &parse, tokens );
-
-   while( !tgsi_parse_end_of_tokens( &parse ) ) {
-
-      tgsi_parse_token( &parse );
+   switch( token->Token.Type ) {
+   case TGSI_TOKEN_TYPE_PROPERTY:
+      /*
+       * We only support one cbuf, but we still need to ignore the property
+       * correctly so we don't hit the assert at the end of the switch case.
+       */
+      assert(token->FullProperty.Property.PropertyName ==
+             TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS);
+      break;
 
-      switch( parse.FullToken.Token.Type ) {
-      case TGSI_TOKEN_TYPE_PROPERTY:
-         /*
-          * We only support one cbuf, but we still need to ignore the property
-          * correctly so we don't hit the assert at the end of the switch case.
-          */
-         assert(parse.FullToken.FullProperty.Property.PropertyName ==
-                TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS);
-         break;
-      case TGSI_TOKEN_TYPE_DECLARATION:
-         if (parse.FullToken.FullDeclaration.Declaration.File
-                  == TGSI_FILE_CONSTANT) {
-            uint i;
-            for (i = parse.FullToken.FullDeclaration.Range.First;
-                 i <= parse.FullToken.FullDeclaration.Range.Last;
-                 i++) {
-               assert(ifs->constant_flags[i] == 0x0);
-               ifs->constant_flags[i] = I915_CONSTFLAG_USER;
-               ifs->num_constants = MAX2(ifs->num_constants, i + 1);
-            }
+   case TGSI_TOKEN_TYPE_DECLARATION:
+      if (token->FullDeclaration.Declaration.File
+               == TGSI_FILE_CONSTANT) {
+         uint i;
+         for (i = token->FullDeclaration.Range.First;
+              i <= token->FullDeclaration.Range.Last;
+              i++) {
+            assert(ifs->constant_flags[i] == 0x0);
+            ifs->constant_flags[i] = I915_CONSTFLAG_USER;
+            ifs->num_constants = MAX2(ifs->num_constants, i + 1);
          }
-         else if (parse.FullToken.FullDeclaration.Declaration.File
-                  == TGSI_FILE_TEMPORARY) {
-            uint i;
-            for (i = parse.FullToken.FullDeclaration.Range.First;
-                 i <= parse.FullToken.FullDeclaration.Range.Last;
-                 i++) {
-               if (i >= I915_MAX_TEMPORARY)
-                  debug_printf("Too many temps (%d)\n",i);
-	       else
-                  /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
-                  p->temp_flag |= (1 << i); /* mark temp as used */
-            }
+      }
+      else if (token->FullDeclaration.Declaration.File
+               == TGSI_FILE_TEMPORARY) {
+         uint i;
+         for (i = token->FullDeclaration.Range.First;
+              i <= token->FullDeclaration.Range.Last;
+              i++) {
+            if (i >= I915_MAX_TEMPORARY)
+               debug_printf("Too many temps (%d)\n",i);
+            else
+               /* XXX just use shader->info->file_mask[TGSI_FILE_TEMPORARY] */
+               p->temp_flag |= (1 << i); /* mark temp as used */
          }
-         break;
+      }
+      break;
 
-      case TGSI_TOKEN_TYPE_IMMEDIATE:
-         {
-            const struct tgsi_full_immediate *imm
-               = &parse.FullToken.FullImmediate;
-            const uint pos = p->num_immediates++;
-            uint j;
-            assert( imm->Immediate.NrTokens <= 4 + 1 );
-            for (j = 0; j < imm->Immediate.NrTokens - 1; j++) {
-               p->immediates[pos][j] = imm->u[j].Float;
-            }
+   case TGSI_TOKEN_TYPE_IMMEDIATE:
+      {
+         const struct tgsi_full_immediate *imm
+            = &token->FullImmediate;
+         const uint pos = p->num_immediates++;
+         uint j;
+         assert( imm->Immediate.NrTokens <= 4 + 1 );
+         for (j = 0; j < imm->Immediate.NrTokens - 1; j++) {
+            p->immediates[pos][j] = imm->u[j].Float;
          }
-         break;
+      }
+      break;
 
-      case TGSI_TOKEN_TYPE_INSTRUCTION:
-         if (p->first_instruction) {
-            /* resolve location of immediates */
-            uint i, j;
-            for (i = 0; i < p->num_immediates; i++) {
-               /* find constant slot for this immediate */
-               for (j = 0; j < I915_MAX_CONSTANT; j++) {
-                  if (ifs->constant_flags[j] == 0x0) {
-                     memcpy(ifs->constants[j],
-                            p->immediates[i],
-                            4 * sizeof(float));
-                     /*printf("immediate %d maps to const %d\n", i, j);*/
-                     ifs->constant_flags[j] = 0xf;  /* all four comps used */
-                     p->immediates_map[i] = j;
-                     ifs->num_constants = MAX2(ifs->num_constants, j + 1);
-                     break;
-                  }
+   case TGSI_TOKEN_TYPE_INSTRUCTION:
+      if (p->first_instruction) {
+         /* resolve location of immediates */
+         uint i, j;
+         for (i = 0; i < p->num_immediates; i++) {
+            /* find constant slot for this immediate */
+            for (j = 0; j < I915_MAX_CONSTANT; j++) {
+               if (ifs->constant_flags[j] == 0x0) {
+                  memcpy(ifs->constants[j],
+                         p->immediates[i],
+                         4 * sizeof(float));
+                  /*printf("immediate %d maps to const %d\n", i, j);*/
+                  ifs->constant_flags[j] = 0xf;  /* all four comps used */
+                  p->immediates_map[i] = j;
+                  ifs->num_constants = MAX2(ifs->num_constants, j + 1);
+                  break;
                }
             }
-
-            p->first_instruction = FALSE;
          }
 
-         i915_translate_instruction(p, &parse.FullToken.FullInstruction, fs);
-         break;
-
-      default:
-         assert( 0 );
+         p->first_instruction = FALSE;
       }
 
-   } /* while */
+      i915_translate_instruction(p, &token->FullInstruction, fs);
+      break;
+
+   default:
+      assert( 0 );
+   }
 
-   tgsi_parse_free (&parse);
+}
+
+/**
+ * Translate TGSI fragment shader into i915 hardware instructions.
+ * \param p  the translation state
+ * \param tokens  the TGSI token array
+ */
+static void
+i915_translate_instructions(struct i915_fp_compile *p,
+                            const struct i915_token_list *tokens,
+                            struct i915_fragment_shader *fs)
+{
+   int i;
+   for(i = 0; i<tokens->NumTokens; i++) {
+      i915_translate_token(p, &tokens->Tokens[i], fs);
+   }
 }
 
 
@@ -1302,8 +1306,10 @@ i915_translate_fragment_program( struct i915_context *i915,
 
    p = i915_init_compile(i915, fs);
 
-   i915_translate_instructions(p, tokens, fs);
+   struct i915_token_list* i_tokens = i915_optimize(tokens);
+   i915_translate_instructions(p, i_tokens, fs);
    i915_fixup_depth_write(p);
 
    i915_fini_compile(i915, p);
+   i915_optimize_free(i_tokens);
 }
diff --git a/src/gallium/drivers/i915/i915_prim_emit.c b/src/gallium/drivers/i915/i915_prim_emit.c
index 85656cd7846..1acde97d4bd 100644
--- a/src/gallium/drivers/i915/i915_prim_emit.c
+++ b/src/gallium/drivers/i915/i915_prim_emit.c
@@ -166,6 +166,8 @@ emit_prim( struct draw_stage *stage,
 
    for (i = 0; i < nr; i++)
       emit_hw_vertex(i915, prim->v[i]);
+
+   i915_flush_heuristically(i915, nr);
 }
 
 
diff --git a/src/gallium/drivers/i915/i915_prim_vbuf.c b/src/gallium/drivers/i915/i915_prim_vbuf.c
index 79db3b650eb..d8ae1de2963 100644
--- a/src/gallium/drivers/i915/i915_prim_vbuf.c
+++ b/src/gallium/drivers/i915/i915_prim_vbuf.c
@@ -487,6 +487,7 @@ draw_arrays_fallback(struct vbuf_render *render,
 
    draw_arrays_generate_indices(render, start, nr, i915_render->fallback);
 
+   i915_flush_heuristically(i915, nr_indices);
 out:
    return;
 }
@@ -534,6 +535,7 @@ i915_vbuf_render_draw_arrays(struct vbuf_render *render,
              nr);
    OUT_BATCH(start); /* Beginning vertex index */
 
+   i915_flush_heuristically(i915, nr);
 out:
    return;
 }
@@ -657,6 +659,7 @@ i915_vbuf_render_draw_elements(struct vbuf_render *render,
                          save_nr_indices,
                          i915_render->fallback);
 
+   i915_flush_heuristically(i915, nr_indices);
 out:
    return;
 }
diff --git a/src/gallium/drivers/i915/i915_state.c b/src/gallium/drivers/i915/i915_state.c
index f412626955d..2812de1fe80 100644
--- a/src/gallium/drivers/i915/i915_state.c
+++ b/src/gallium/drivers/i915/i915_state.c
@@ -244,7 +244,7 @@ i915_create_sampler_state(struct pipe_context *pipe,
 
    /* Shadow:
     */
-   if (sampler->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) 
+   if (sampler->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
    {
       cso->state[0] |= (SS2_SHADOW_ENABLE |
                         i915_translate_shadow_compare_func(sampler->compare_func));
diff --git a/src/gallium/drivers/i915/i915_state_emit.c b/src/gallium/drivers/i915/i915_state_emit.c
index 39fb13aec7e..4f447962bb9 100644
--- a/src/gallium/drivers/i915/i915_state_emit.c
+++ b/src/gallium/drivers/i915/i915_state_emit.c
@@ -346,97 +346,80 @@ emit_constants(struct i915_context *i915)
 static const struct
 {
    enum pipe_format format;
-   uint hw_shift_R;
-   uint hw_shift_G;
-   uint hw_shift_B;
-   uint hw_shift_A;
+   uint hw_swizzle;
 } fixup_formats[] = {
-   { PIPE_FORMAT_R8G8B8A8_UNORM, 20, 24, 28, 16 /* BGRA */},
-   { PIPE_FORMAT_L8_UNORM,       28, 28, 28, 16 /* RRRA */},
-   { PIPE_FORMAT_I8_UNORM,       28, 28, 28, 16 /* RRRA */},
-   { PIPE_FORMAT_A8_UNORM,       16, 16, 16, 16 /* AAAA */},
-   { PIPE_FORMAT_NONE,           0,   0,  0,  0},
+   { PIPE_FORMAT_R8G8B8A8_UNORM, 0x21030000 /* BGRA */},
+   { PIPE_FORMAT_L8_UNORM,       0x00030000 /* RRRA */},
+   { PIPE_FORMAT_I8_UNORM,       0x00030000 /* RRRA */},
+   { PIPE_FORMAT_A8_UNORM,       0x33330000 /* AAAA */},
+   { PIPE_FORMAT_NONE,           0x00000000},
 };
 
-static boolean need_fixup(struct pipe_surface* p)
+static uint need_target_fixup(struct pipe_surface* p)
 {
    enum pipe_format f;
-
    /* if we don't have a surface bound yet, we don't need to fixup the shader */
    if (!p)
-      return FALSE;
+      return 0;
 
    f = p->format;
    for(int i=0; fixup_formats[i].format != PIPE_FORMAT_NONE; i++)
       if (fixup_formats[i].format == f)
-         return TRUE;
+         return 1;
 
-   return FALSE;
+   return 0;
 }
 
-static uint fixup_swizzle(enum pipe_format f, uint v)
+static uint fixup_swizzle(enum pipe_format f)
 {
-   int i;
-
-   for(i=0; fixup_formats[i].format != PIPE_FORMAT_NONE; i++)
+   for(int i=0; fixup_formats[i].format != PIPE_FORMAT_NONE; i++)
       if (fixup_formats[i].format == f)
-           break;
-
-   if (fixup_formats[i].format == PIPE_FORMAT_NONE)
-	   return v;
-
-   uint rgba = v & 0xFFFF0000;
+         return fixup_formats[i].hw_swizzle;
 
-   v &= 0xFFFF;
-   v |= ((rgba >> fixup_formats[i].hw_shift_R) & 0xF) << 28;
-   v |= ((rgba >> fixup_formats[i].hw_shift_G) & 0xF) << 24;
-   v |= ((rgba >> fixup_formats[i].hw_shift_B) & 0xF) << 20;
-   v |= ((rgba >> fixup_formats[i].hw_shift_A) & 0xF) << 16;
-
-   return v;
+   return 0;
 }
 
 static void
 validate_program(struct i915_context *i915, unsigned *batch_space)
 {
-   *batch_space = i915->fs->program_len;
+   struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
+   uint additional_size = need_target_fixup(cbuf_surface);
+
+   /* we need more batch space if we want to emulate rgba framebuffers */
+   *batch_space = i915->fs->program_len + 3 * additional_size;
 }
 
 static void
 emit_program(struct i915_context *i915)
 {
    struct pipe_surface *cbuf_surface = i915->framebuffer.cbufs[0];
-   boolean need_format_fixup = need_fixup(cbuf_surface);
-   int i;
-   int fixup_offset = -1;
+   uint target_fixup = need_target_fixup(cbuf_surface);
+   uint i;
 
    /* we should always have, at least, a pass-through program */
    assert(i915->fs->program_len > 0);
 
-   if (need_format_fixup) {
-      /* Find where we emit the output color */
-      for (i = i915->fs->program_len - 3; i>0; i-=3) {
-         uint instr = i915->fs->program[i];
-         if ((instr & (REG_NR_MASK << A0_DEST_TYPE_SHIFT)) == 
-             (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) ) {
-            /* Found it! */
-            fixup_offset = i + 1;
-            break;
-	 }
-      }
-      if (fixup_offset == -1) {
-         need_format_fixup = FALSE;
-         debug_printf("couldn't find fixup offset\n");
-      }
+   {
+      /* first word has the size, we have to adjust that */
+      uint size = (i915->fs->program[0]);
+      size += target_fixup * 3;
+      OUT_BATCH(size);
    }
 
-   /* emit the program to the hw */
-   for (i = 0; i < i915->fs->program_len; i++) {
-      if (need_format_fixup && (i == fixup_offset) ) {
-         uint v = fixup_swizzle(cbuf_surface->format, i915->fs->program[i]);
-         OUT_BATCH(v);
-      } else
-         OUT_BATCH(i915->fs->program[i]);
+   /* output the declarations of the program */
+   for (i=1 ; i < i915->fs->program_len; i++) 
+      OUT_BATCH(i915->fs->program[i]);
+
+   /* we emit an additional mov with swizzle to fake RGBA framebuffers */
+   if (target_fixup) {
+      /* mov out_color, out_color.zyxw */
+      OUT_BATCH(A0_MOV |
+                (REG_TYPE_OC << A0_DEST_TYPE_SHIFT) |
+                A0_DEST_CHANNEL_ALL |
+                (REG_TYPE_OC << A0_SRC0_TYPE_SHIFT) |
+                (T_DIFFUSE << A0_SRC0_NR_SHIFT));
+      OUT_BATCH(fixup_swizzle(cbuf_surface->format));
+      OUT_BATCH(0);
    }
 }
 
diff --git a/src/gallium/drivers/i915/i915_winsys.h b/src/gallium/drivers/i915/i915_winsys.h
index 21cfdc9613e..20438609e07 100644
--- a/src/gallium/drivers/i915/i915_winsys.h
+++ b/src/gallium/drivers/i915/i915_winsys.h
@@ -207,6 +207,12 @@ struct i915_winsys {
 
    void (*buffer_destroy)(struct i915_winsys *iws,
                           struct i915_winsys_buffer *buffer);
+
+   /**
+    * Check if a buffer is busy.
+    */
+   boolean (*buffer_is_busy)(struct i915_winsys *iws,
+                             struct i915_winsys_buffer *buffer);
    /*@}*/
 
 
diff --git a/src/gallium/drivers/nv50/nv50_context.c b/src/gallium/drivers/nv50/nv50_context.c
index ceb83f6e684..ac3e361a446 100644
--- a/src/gallium/drivers/nv50/nv50_context.c
+++ b/src/gallium/drivers/nv50/nv50_context.c
@@ -60,13 +60,13 @@ nv50_texture_barrier(struct pipe_context *pipe)
 void
 nv50_default_flush_notify(struct nouveau_channel *chan)
 {
-   struct nv50_context *nv50 = chan->user_private;
+   struct nv50_screen *screen = chan->user_private;
 
-   if (!nv50)
+   if (!screen)
       return;
 
-   nouveau_fence_update(&nv50->screen->base, TRUE);
-   nouveau_fence_next(&nv50->screen->base);
+   nouveau_fence_update(&screen->base, TRUE);
+   nouveau_fence_next(&screen->base);
 }
 
 static void
@@ -100,10 +100,8 @@ nv50_destroy(struct pipe_context *pipe)
 
    draw_destroy(nv50->draw);
 
-   if (nv50->screen->cur_ctx == nv50) {
-      nv50->screen->base.channel->user_private = NULL;
+   if (nv50->screen->cur_ctx == nv50)
       nv50->screen->cur_ctx = NULL;
-   }
 
    FREE(nv50);
 }
@@ -140,7 +138,6 @@ nv50_create(struct pipe_screen *pscreen, void *priv)
 
    if (!screen->cur_ctx)
       screen->cur_ctx = nv50;
-   screen->base.channel->user_private = nv50;
    screen->base.channel->flush_notify = nv50_default_flush_notify;
 
    nv50_init_query_functions(nv50);
diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c
index cc921d08666..4cda303c44a 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -215,6 +215,7 @@ nv50_screen_destroy(struct pipe_screen *pscreen)
       nouveau_fence_wait(screen->base.fence.current);
       nouveau_fence_ref (NULL, &screen->base.fence.current);
    }
+   screen->base.channel->user_private = NULL;
 
    nouveau_bo_ref(NULL, &screen->code);
    nouveau_bo_ref(NULL, &screen->tls_bo);
@@ -300,6 +301,7 @@ nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
       FAIL_SCREEN_INIT("nouveau_screen_init failed: %d\n", ret);
 
    chan = screen->base.channel;
+   chan->user_private = screen;
 
    pscreen->winsys = ws;
    pscreen->destroy = nv50_screen_destroy;
diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c b/src/gallium/drivers/nv50/nv50_state_validate.c
index 11561f5a8e6..d29c1e9723f 100644
--- a/src/gallium/drivers/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nv50/nv50_state_validate.c
@@ -282,8 +282,7 @@ nv50_switch_pipe_context(struct nv50_context *ctx_to)
    if (!ctx_to->zsa)
       ctx_to->dirty &= ~NV50_NEW_ZSA;
 
-   ctx_to->screen->base.channel->user_private = ctx_to->screen->cur_ctx =
-      ctx_to;
+   ctx_to->screen->cur_ctx = ctx_to;
 }
 
 static struct state_validate {
diff --git a/src/gallium/drivers/nv50/nv50_surface.c b/src/gallium/drivers/nv50/nv50_surface.c
index 3d7e880ccce..fb51db84ac6 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -34,25 +34,16 @@
 
 #include "nv50_defs.xml.h"
 
+#define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
+
 /* return TRUE for formats that can be converted among each other by NV50_2D */
 static INLINE boolean
 nv50_2d_format_faithful(enum pipe_format format)
 {
-   switch (format) {
-   case PIPE_FORMAT_B8G8R8A8_UNORM:
-   case PIPE_FORMAT_B8G8R8X8_UNORM:
-   case PIPE_FORMAT_B8G8R8A8_SRGB:
-   case PIPE_FORMAT_B8G8R8X8_SRGB:
-   case PIPE_FORMAT_B5G6R5_UNORM:
-   case PIPE_FORMAT_B5G5R5A1_UNORM:
-   case PIPE_FORMAT_B10G10R10A2_UNORM:
-   case PIPE_FORMAT_R8_UNORM:
-   case PIPE_FORMAT_R32G32B32A32_FLOAT:
-   case PIPE_FORMAT_R32G32B32_FLOAT:
-      return TRUE;
-   default:
-      return FALSE;
-   }
+   uint8_t id = nv50_format_table[format].rt;
+
+   return (id >= 0xc0) &&
+      (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0)));
 }
 
 static INLINE uint8_t
@@ -63,7 +54,7 @@ nv50_2d_format(enum pipe_format format)
    /* Hardware values for color formats range from 0xc0 to 0xff,
     * but the 2D engine doesn't support all of them.
     */
-   if ((id >= 0xc0) && (0xff0843e080608409ULL & (1ULL << (id - 0xc0))))
+   if ((id >= 0xc0) && (NV50_ENG2D_SUPPORTED_FORMATS & (1ULL << (id - 0xc0))))
       return id;
 
    switch (util_format_get_blocksize(format)) {
diff --git a/src/gallium/drivers/nv50/nv50_vbo.c b/src/gallium/drivers/nv50/nv50_vbo.c
index bb08941c243..f23008ae4cf 100644
--- a/src/gallium/drivers/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nv50/nv50_vbo.c
@@ -389,11 +389,11 @@ nv50_prim_gl(unsigned prim)
 static void
 nv50_draw_vbo_flush_notify(struct nouveau_channel *chan)
 {
-   struct nv50_context *nv50 = chan->user_private;
+   struct nv50_screen *screen = chan->user_private;
 
-   nouveau_fence_update(&nv50->screen->base, TRUE);
+   nouveau_fence_update(&screen->base, TRUE);
 
-   nv50_bufctx_emit_relocs(nv50);
+   nv50_bufctx_emit_relocs(screen->cur_ctx);
 }
 
 static void
@@ -650,7 +650,6 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
    nv50_state_validate(nv50);
 
    chan->flush_notify = nv50_draw_vbo_flush_notify;
-   chan->user_private = nv50;
 
    if (nv50->vbo_fifo) {
       nv50_push_vbo(nv50, info);
diff --git a/src/gallium/drivers/nvc0/nvc0_context.c b/src/gallium/drivers/nvc0/nvc0_context.c
index 2679b7f86aa..983db23eedb 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nvc0/nvc0_context.c
@@ -89,10 +89,8 @@ nvc0_destroy(struct pipe_context *pipe)
 
    draw_destroy(nvc0->draw);
 
-   if (nvc0->screen->cur_ctx == nvc0) {
-      nvc0->screen->base.channel->user_private = NULL;
+   if (nvc0->screen->cur_ctx == nvc0)
       nvc0->screen->cur_ctx = NULL;
-   }
 
    FREE(nvc0);
 }
@@ -100,13 +98,13 @@ nvc0_destroy(struct pipe_context *pipe)
 void
 nvc0_default_flush_notify(struct nouveau_channel *chan)
 {
-   struct nvc0_context *nvc0 = chan->user_private;
+   struct nvc0_screen *screen = chan->user_private;
 
-   if (!nvc0)
+   if (!screen)
       return;
 
-   nouveau_fence_update(&nvc0->screen->base, TRUE);
-   nouveau_fence_next(&nvc0->screen->base);
+   nouveau_fence_update(&screen->base, TRUE);
+   nouveau_fence_next(&screen->base);
 }
 
 struct pipe_context *
@@ -141,7 +139,6 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
 
    if (!screen->cur_ctx)
       screen->cur_ctx = nvc0;
-   screen->base.channel->user_private = nvc0;
    screen->base.channel->flush_notify = nvc0_default_flush_notify;
 
    nvc0_init_query_functions(nvc0);
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c
index 34bf0f0a2ad..1bd7fa9f0ea 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -198,8 +198,11 @@ nvc0_screen_destroy(struct pipe_screen *pscreen)
 {
    struct nvc0_screen *screen = nvc0_screen(pscreen);
 
-   nouveau_fence_wait(screen->base.fence.current);
-   nouveau_fence_ref(NULL, &screen->base.fence.current);
+   if (screen->base.fence.current) {
+      nouveau_fence_wait(screen->base.fence.current);
+      nouveau_fence_ref(NULL, &screen->base.fence.current);
+   }
+   screen->base.channel->user_private = NULL;
 
    nouveau_bo_ref(NULL, &screen->text);
    nouveau_bo_ref(NULL, &screen->tls);
@@ -358,6 +361,7 @@ nvc0_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
       return NULL;
    }
    chan = screen->base.channel;
+   chan->user_private = screen;
 
    pscreen->winsys = ws;
    pscreen->destroy = nvc0_screen_destroy;
diff --git a/src/gallium/drivers/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nvc0/nvc0_state_validate.c
index 9b2a28150b1..f300f37fb7b 100644
--- a/src/gallium/drivers/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nvc0/nvc0_state_validate.c
@@ -428,8 +428,7 @@ nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
    if (!ctx_to->zsa)
       ctx_to->dirty &= ~NVC0_NEW_ZSA;
 
-   ctx_to->screen->base.channel->user_private = ctx_to->screen->cur_ctx =
-      ctx_to;
+   ctx_to->screen->cur_ctx = ctx_to;
 }
 
 static struct state_validate {
diff --git a/src/gallium/drivers/nvc0/nvc0_vbo.c b/src/gallium/drivers/nvc0/nvc0_vbo.c
index 41079104b39..8a5bf8dc582 100644
--- a/src/gallium/drivers/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nvc0/nvc0_vbo.c
@@ -367,11 +367,11 @@ nvc0_prim_gl(unsigned prim)
 static void
 nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
 {
-   struct nvc0_context *nvc0 = chan->user_private;
+   struct nvc0_screen *screen = chan->user_private;
 
-   nouveau_fence_update(&nvc0->screen->base, TRUE);
+   nouveau_fence_update(&screen->base, TRUE);
 
-   nvc0_bufctx_emit_relocs(nvc0);
+   nvc0_bufctx_emit_relocs(screen->cur_ctx);
 }
 
 static void
@@ -587,7 +587,6 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
    nvc0_state_validate(nvc0);
 
    chan->flush_notify = nvc0_draw_vbo_flush_notify;
-   chan->user_private = nvc0;
 
    if (nvc0->vbo_fifo) {
       nvc0_push_vbo(nvc0, info);
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index fb0b0f104bf..c95872b0809 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -69,7 +69,7 @@ int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 			S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst);
-		if (bc->chiprev == CHIPREV_EVERGREEN) /* no EOP on cayman */
+		if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
 			bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
 		id++;
 
diff --git a/src/gallium/drivers/r600/eg_state_inlines.h b/src/gallium/drivers/r600/eg_state_inlines.h
deleted file mode 100644
index b5590116e8f..00000000000
--- a/src/gallium/drivers/r600/eg_state_inlines.h
+++ /dev/null
@@ -1,587 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef EG_STATE_INLINES_H
-#define EG_STATE_INLINES_H
-
-#include "util/u_format.h"
-#include "evergreend.h"
-#include "r600_formats.h"
-
-static INLINE uint32_t r600_translate_blend_function(int blend_func)
-{
-	switch (blend_func) {
-	case PIPE_BLEND_ADD:
-		return V_028780_COMB_DST_PLUS_SRC;
-	case PIPE_BLEND_SUBTRACT:
-		return V_028780_COMB_SRC_MINUS_DST;
-	case PIPE_BLEND_REVERSE_SUBTRACT:
-		return V_028780_COMB_DST_MINUS_SRC;
-	case PIPE_BLEND_MIN:
-		return V_028780_COMB_MIN_DST_SRC;
-	case PIPE_BLEND_MAX:
-		return V_028780_COMB_MAX_DST_SRC;
-	default:
-		R600_ERR("Unknown blend function %d\n", blend_func);
-		assert(0);
-		break;
-	}
-	return 0;
-}
-
-static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
-{
-	switch (blend_fact) {
-	case PIPE_BLENDFACTOR_ONE:
-		return V_028780_BLEND_ONE;
-	case PIPE_BLENDFACTOR_SRC_COLOR:
-		return V_028780_BLEND_SRC_COLOR;
-	case PIPE_BLENDFACTOR_SRC_ALPHA:
-		return V_028780_BLEND_SRC_ALPHA;
-	case PIPE_BLENDFACTOR_DST_ALPHA:
-		return V_028780_BLEND_DST_ALPHA;
-	case PIPE_BLENDFACTOR_DST_COLOR:
-		return V_028780_BLEND_DST_COLOR;
-	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
-		return V_028780_BLEND_SRC_ALPHA_SATURATE;
-	case PIPE_BLENDFACTOR_CONST_COLOR:
-		return V_028780_BLEND_CONST_COLOR;
-	case PIPE_BLENDFACTOR_CONST_ALPHA:
-		return V_028780_BLEND_CONST_ALPHA;
-	case PIPE_BLENDFACTOR_ZERO:
-		return V_028780_BLEND_ZERO;
-	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
-		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
-	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
-		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
-	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
-		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
-	case PIPE_BLENDFACTOR_INV_DST_COLOR:
-		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
-	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
-		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
-	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
-		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
-	case PIPE_BLENDFACTOR_SRC1_COLOR:
-		return V_028780_BLEND_SRC1_COLOR;
-	case PIPE_BLENDFACTOR_SRC1_ALPHA:
-		return V_028780_BLEND_SRC1_ALPHA;
-	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
-		return V_028780_BLEND_INV_SRC1_COLOR;
-	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
-		return V_028780_BLEND_INV_SRC1_ALPHA;
-	default:
-		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
-		assert(0);
-		break;
-	}
-	return 0;
-}
-
-static INLINE uint32_t r600_translate_stencil_op(int s_op)
-{
-	switch (s_op) {
-	case PIPE_STENCIL_OP_KEEP:
-		return V_028800_STENCIL_KEEP;
-	case PIPE_STENCIL_OP_ZERO:
-		return V_028800_STENCIL_ZERO;
-	case PIPE_STENCIL_OP_REPLACE:
-		return V_028800_STENCIL_REPLACE;
-	case PIPE_STENCIL_OP_INCR:
-		return V_028800_STENCIL_INCR;
-	case PIPE_STENCIL_OP_DECR:
-		return V_028800_STENCIL_DECR;
-	case PIPE_STENCIL_OP_INCR_WRAP:
-		return V_028800_STENCIL_INCR_WRAP;
-	case PIPE_STENCIL_OP_DECR_WRAP:
-		return V_028800_STENCIL_DECR_WRAP;
-	case PIPE_STENCIL_OP_INVERT:
-		return V_028800_STENCIL_INVERT;
-	default:
-		R600_ERR("Unknown stencil op %d", s_op);
-		assert(0);
-		break;
-	}
-	return 0;
-}
-
-static INLINE uint32_t r600_translate_fill(uint32_t func)
-{
-	switch(func) {
-	case PIPE_POLYGON_MODE_FILL:
-		return 2;
-	case PIPE_POLYGON_MODE_LINE:
-		return 1;
-	case PIPE_POLYGON_MODE_POINT:
-		return 0;
-	default:
-		assert(0);
-		return 0;
-	}
-}
-
-/* translates straight */
-static INLINE uint32_t r600_translate_ds_func(int func)
-{
-	return func;
-}
-
-static inline unsigned r600_tex_wrap(unsigned wrap)
-{
-	switch (wrap) {
-	default:
-	case PIPE_TEX_WRAP_REPEAT:
-		return V_03C000_SQ_TEX_WRAP;
-	case PIPE_TEX_WRAP_CLAMP:
-		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
-	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
-		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
-	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
-		return V_03C000_SQ_TEX_CLAMP_BORDER;
-	case PIPE_TEX_WRAP_MIRROR_REPEAT:
-		return V_03C000_SQ_TEX_MIRROR;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
-	}
-}
-
-static inline unsigned r600_tex_filter(unsigned filter)
-{
-	switch (filter) {
-	default:
-	case PIPE_TEX_FILTER_NEAREST:
-		return V_03C000_SQ_TEX_XY_FILTER_POINT;
-	case PIPE_TEX_FILTER_LINEAR:
-		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
-	}
-}
-
-static inline unsigned r600_tex_mipfilter(unsigned filter)
-{
-	switch (filter) {
-	case PIPE_TEX_MIPFILTER_NEAREST:
-		return V_03C000_SQ_TEX_Z_FILTER_POINT;
-	case PIPE_TEX_MIPFILTER_LINEAR:
-		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
-	default:
-	case PIPE_TEX_MIPFILTER_NONE:
-		return V_03C000_SQ_TEX_Z_FILTER_NONE;
-	}
-}
-
-static inline unsigned r600_tex_compare(unsigned compare)
-{
-	switch (compare) {
-	default:
-	case PIPE_FUNC_NEVER:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
-	case PIPE_FUNC_LESS:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
-	case PIPE_FUNC_EQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
-	case PIPE_FUNC_LEQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
-	case PIPE_FUNC_GREATER:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
-	case PIPE_FUNC_NOTEQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
-	case PIPE_FUNC_GEQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
-	case PIPE_FUNC_ALWAYS:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
-	}
-}
-
-static inline unsigned r600_tex_swizzle(unsigned swizzle)
-{
-	switch (swizzle) {
-	case PIPE_SWIZZLE_RED:
-		return V_030010_SQ_SEL_X;
-	case PIPE_SWIZZLE_GREEN:
-		return V_030010_SQ_SEL_Y;
-	case PIPE_SWIZZLE_BLUE:
-		return V_030010_SQ_SEL_Z;
-	case PIPE_SWIZZLE_ALPHA:
-		return V_030010_SQ_SEL_W;
-	case PIPE_SWIZZLE_ZERO:
-		return V_030010_SQ_SEL_0;
-	default:
-	case PIPE_SWIZZLE_ONE:
-		return V_030010_SQ_SEL_1;
-	}
-}
-
-static inline unsigned r600_format_type(unsigned format_type)
-{
-	switch (format_type) {
-	default:
-	case UTIL_FORMAT_TYPE_UNSIGNED:
-		return V_030010_SQ_FORMAT_COMP_UNSIGNED;
-	case UTIL_FORMAT_TYPE_SIGNED:
-		return V_030010_SQ_FORMAT_COMP_SIGNED;
-	case UTIL_FORMAT_TYPE_FIXED:
-		return V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
-	}
-}
-
-static inline unsigned r600_tex_dim(unsigned dim)
-{
-	switch (dim) {
-	default:
-	case PIPE_TEXTURE_1D:
-		return V_030000_SQ_TEX_DIM_1D;
-	case PIPE_TEXTURE_1D_ARRAY:
-		return V_030000_SQ_TEX_DIM_1D_ARRAY;
-	case PIPE_TEXTURE_2D:
-	case PIPE_TEXTURE_RECT:
-		return V_030000_SQ_TEX_DIM_2D;
-	case PIPE_TEXTURE_2D_ARRAY:
-		return V_030000_SQ_TEX_DIM_2D_ARRAY;
-	case PIPE_TEXTURE_3D:
-		return V_030000_SQ_TEX_DIM_3D;
-	case PIPE_TEXTURE_CUBE:
-		return V_030000_SQ_TEX_DIM_CUBEMAP;
-	}
-}
-
-static inline uint32_t r600_translate_dbformat(enum pipe_format format)
-{
-	switch (format) {
-	case PIPE_FORMAT_Z16_UNORM:
-		return V_028040_Z_16;
-	case PIPE_FORMAT_Z24X8_UNORM:
-		return V_028040_Z_24;
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return V_028040_Z_24;
-	default:
-		return ~0;
-	}
-}
-
-static inline uint32_t r600_translate_stencilformat(enum pipe_format format)
-{
-	if (format == PIPE_FORMAT_Z24_UNORM_S8_USCALED)
-		return 1;
-	else
-		return 0;
-}
-
-static inline uint32_t r600_translate_colorswap(enum pipe_format format)
-{
-	switch (format) {
-	/* 8-bit buffers. */
-	case PIPE_FORMAT_L4A4_UNORM:
-		return V_028C70_SWAP_ALT;
-
-	case PIPE_FORMAT_A8_UNORM:
-		return V_028C70_SWAP_ALT_REV;
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_L8_SRGB:
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R8_SNORM:
-		return V_028C70_SWAP_STD;
-
-	/* 16-bit buffers. */
-	case PIPE_FORMAT_B5G6R5_UNORM:
-		return V_028C70_SWAP_STD_REV;
-
-	case PIPE_FORMAT_B5G5R5A1_UNORM:
-	case PIPE_FORMAT_B5G5R5X1_UNORM:
-		return V_028C70_SWAP_ALT;
-
-	case PIPE_FORMAT_B4G4R4A4_UNORM:
-	case PIPE_FORMAT_B4G4R4X4_UNORM:
-		return V_028C70_SWAP_ALT;
-
-	case PIPE_FORMAT_Z16_UNORM:
-		return V_028C70_SWAP_STD;
-
-	case PIPE_FORMAT_L8A8_UNORM:
-	case PIPE_FORMAT_L8A8_SRGB:
-		return V_028C70_SWAP_ALT;
-	case PIPE_FORMAT_R8G8_UNORM:
-		return V_028C70_SWAP_STD;
-
-	case PIPE_FORMAT_R16_UNORM:
-	case PIPE_FORMAT_R16_FLOAT:
-		return V_028C70_SWAP_STD;
-
-	/* 32-bit buffers. */
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-		return V_028C70_SWAP_STD_REV;
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
-		return V_028C70_SWAP_ALT;
-
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-		return V_028C70_SWAP_ALT;
-
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-		return V_028C70_SWAP_ALT_REV;
-	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-		return V_028C70_SWAP_STD;
-
-	case PIPE_FORMAT_A8B8G8R8_UNORM:
-	case PIPE_FORMAT_X8B8G8R8_UNORM:
-	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
-		return V_028C70_SWAP_STD_REV;
-
-	case PIPE_FORMAT_Z24X8_UNORM:
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return V_028C70_SWAP_STD;
-
-	case PIPE_FORMAT_X8Z24_UNORM:
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-		return V_028C70_SWAP_STD;
-
-	case PIPE_FORMAT_R10G10B10A2_UNORM:
-	case PIPE_FORMAT_R10G10B10X2_SNORM:
-	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
-		return V_028C70_SWAP_STD;
-
-	case PIPE_FORMAT_B10G10R10A2_UNORM:
-		return V_028C70_SWAP_ALT;
-
-	case PIPE_FORMAT_R11G11B10_FLOAT:
-	case PIPE_FORMAT_R32_FLOAT:
-	case PIPE_FORMAT_R16G16_FLOAT:
-	case PIPE_FORMAT_R16G16_UNORM:
-		return V_028C70_SWAP_STD;
-
-	/* 64-bit buffers. */
-	case PIPE_FORMAT_R32G32_FLOAT:
-	case PIPE_FORMAT_R16G16B16A16_UNORM:
-	case PIPE_FORMAT_R16G16B16A16_SNORM:
-	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-
-	/* 128-bit buffers. */
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-	case PIPE_FORMAT_R32G32B32A32_SNORM:
-	case PIPE_FORMAT_R32G32B32A32_UNORM:
-		return V_028C70_SWAP_STD;
-	default:
-		R600_ERR("unsupported colorswap format %d\n", format);
-		return ~0;
-	}
-	return ~0;
-}
-
-static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
-{
-	switch (format) {
-	/* 8-bit buffers. */
-	case PIPE_FORMAT_L4A4_UNORM:
-		return V_028C70_COLOR_4_4;
-
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_L8_SRGB:
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R8_SNORM:
-		return V_028C70_COLOR_8;
-
-	/* 16-bit buffers. */
-	case PIPE_FORMAT_B5G6R5_UNORM:
-		return V_028C70_COLOR_5_6_5;
-
-	case PIPE_FORMAT_B5G5R5A1_UNORM:
-	case PIPE_FORMAT_B5G5R5X1_UNORM:
-		return V_028C70_COLOR_1_5_5_5;
-
-	case PIPE_FORMAT_B4G4R4A4_UNORM:
-	case PIPE_FORMAT_B4G4R4X4_UNORM:
-		return V_028C70_COLOR_4_4_4_4;
-
-	case PIPE_FORMAT_Z16_UNORM:
-		return V_028C70_COLOR_16;
-
-	case PIPE_FORMAT_L8A8_UNORM:
-	case PIPE_FORMAT_L8A8_SRGB:
-	case PIPE_FORMAT_R8G8_UNORM:
-		return V_028C70_COLOR_8_8;
-
-	case PIPE_FORMAT_R16_UNORM:
-		return V_028C70_COLOR_16;
-
-	case PIPE_FORMAT_R16_FLOAT:
-		return V_028C70_COLOR_16_FLOAT;
-
-	/* 32-bit buffers. */
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-	case PIPE_FORMAT_A8B8G8R8_UNORM:
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
-	case PIPE_FORMAT_X8B8G8R8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_R8G8B8_UNORM:
-		return V_028C70_COLOR_8_8_8_8;
-
-	case PIPE_FORMAT_R10G10B10A2_UNORM:
-	case PIPE_FORMAT_R10G10B10X2_SNORM:
-	case PIPE_FORMAT_B10G10R10A2_UNORM:
-	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
-		return V_028C70_COLOR_2_10_10_10;
-
-	case PIPE_FORMAT_Z24X8_UNORM:
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return V_028C70_COLOR_8_24;
-
-	case PIPE_FORMAT_X8Z24_UNORM:
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-		return V_028C70_COLOR_24_8;
-
-	case PIPE_FORMAT_R32_FLOAT:
-		return V_028C70_COLOR_32_FLOAT;
-
-	case PIPE_FORMAT_R16G16_FLOAT:
-		return V_028C70_COLOR_16_16_FLOAT;
-
-	case PIPE_FORMAT_R16G16_SSCALED:
-	case PIPE_FORMAT_R16G16_UNORM:
-		return V_028C70_COLOR_16_16;
-
-	case PIPE_FORMAT_R11G11B10_FLOAT:
-		return V_028C70_COLOR_10_11_11_FLOAT;
-
-	/* 64-bit buffers. */
-	case PIPE_FORMAT_R16G16B16_USCALED:
-	case PIPE_FORMAT_R16G16B16A16_USCALED:
-	case PIPE_FORMAT_R16G16B16_SSCALED:
-	case PIPE_FORMAT_R16G16B16A16_SSCALED:
-	case PIPE_FORMAT_R16G16B16A16_UNORM:
-	case PIPE_FORMAT_R16G16B16A16_SNORM:
-		return V_028C70_COLOR_16_16_16_16;
-
-	case PIPE_FORMAT_R16G16B16_FLOAT:
-	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-		return V_028C70_COLOR_16_16_16_16_FLOAT;
-
-	case PIPE_FORMAT_R32G32_FLOAT:
-		return V_028C70_COLOR_32_32_FLOAT;
-
-	case PIPE_FORMAT_R32G32_USCALED:
-	case PIPE_FORMAT_R32G32_SSCALED:
-		return V_028C70_COLOR_32_32;
-
-	/* 96-bit buffers. */
-	case PIPE_FORMAT_R32G32B32_FLOAT:
-		return V_028C70_COLOR_32_32_32_FLOAT;
-
-	/* 128-bit buffers. */
-	case PIPE_FORMAT_R32G32B32A32_SNORM:
-	case PIPE_FORMAT_R32G32B32A32_UNORM:
-		return V_028C70_COLOR_32_32_32_32;
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-		return V_028C70_COLOR_32_32_32_32_FLOAT;
-
-	/* YUV buffers. */
-	case PIPE_FORMAT_UYVY:
-	case PIPE_FORMAT_YUYV:
-	default:
-		return ~0; /* Unsupported. */
-	}
-}
-
-static INLINE uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
-{
-	if (R600_BIG_ENDIAN) {
-		switch(colorformat) {
-		case V_028C70_COLOR_4_4:
-			return(ENDIAN_NONE);
-
-		/* 8-bit buffers. */
-		case V_028C70_COLOR_8:
-			return(ENDIAN_NONE);
-
-		/* 16-bit buffers. */
-		case V_028C70_COLOR_5_6_5:
-		case V_028C70_COLOR_1_5_5_5:
-		case V_028C70_COLOR_4_4_4_4:
-		case V_028C70_COLOR_16:
-		case V_028C70_COLOR_8_8:
-			return(ENDIAN_8IN16);
-
-		/* 32-bit buffers. */
-		case V_028C70_COLOR_8_8_8_8:
-		case V_028C70_COLOR_2_10_10_10:
-		case V_028C70_COLOR_8_24:
-		case V_028C70_COLOR_24_8:
-		case V_028C70_COLOR_32_FLOAT:
-		case V_028C70_COLOR_16_16_FLOAT:
-		case V_028C70_COLOR_16_16:
-			return(ENDIAN_8IN32);
-
-		/* 64-bit buffers. */
-		case V_028C70_COLOR_16_16_16_16:
-		case V_028C70_COLOR_16_16_16_16_FLOAT:
-			return(ENDIAN_8IN16);
-
-		case V_028C70_COLOR_32_32_FLOAT:
-		case V_028C70_COLOR_32_32:
-			return(ENDIAN_8IN32);
-
-		/* 96-bit buffers. */
-		case V_028C70_COLOR_32_32_32_FLOAT:
-		/* 128-bit buffers. */
-		case V_028C70_COLOR_32_32_32_32_FLOAT:
-		case V_028C70_COLOR_32_32_32_32:
-			return(ENDIAN_8IN32);
-		default:
-			return ENDIAN_NONE; /* Unsupported. */
-		}
-	} else {
-		return ENDIAN_NONE;
-	}
-}
-
-static INLINE boolean r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
-{
-	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0;
-}
-
-static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format)
-{
-	return r600_translate_colorformat(format) != ~0 &&
-		r600_translate_colorswap(format) != ~0;
-}
-
-static INLINE boolean r600_is_zs_format_supported(enum pipe_format format)
-{
-	return r600_translate_dbformat(format) != ~0;
-}
-
-#endif
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index dc182611482..fbf25feaf20 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -46,7 +46,587 @@
 #include "r600_resource.h"
 #include "r600_shader.h"
 #include "r600_pipe.h"
-#include "eg_state_inlines.h"
+#include "r600_formats.h"
+
+static uint32_t r600_translate_blend_function(int blend_func)
+{
+	switch (blend_func) {
+	case PIPE_BLEND_ADD:
+		return V_028780_COMB_DST_PLUS_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return V_028780_COMB_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return V_028780_COMB_DST_MINUS_SRC;
+	case PIPE_BLEND_MIN:
+		return V_028780_COMB_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return V_028780_COMB_MAX_DST_SRC;
+	default:
+		R600_ERR("Unknown blend function %d\n", blend_func);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static uint32_t r600_translate_blend_factor(int blend_fact)
+{
+	switch (blend_fact) {
+	case PIPE_BLENDFACTOR_ONE:
+		return V_028780_BLEND_ONE;
+	case PIPE_BLENDFACTOR_SRC_COLOR:
+		return V_028780_BLEND_SRC_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA:
+		return V_028780_BLEND_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_DST_ALPHA:
+		return V_028780_BLEND_DST_ALPHA;
+	case PIPE_BLENDFACTOR_DST_COLOR:
+		return V_028780_BLEND_DST_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+		return V_028780_BLEND_SRC_ALPHA_SATURATE;
+	case PIPE_BLENDFACTOR_CONST_COLOR:
+		return V_028780_BLEND_CONST_COLOR;
+	case PIPE_BLENDFACTOR_CONST_ALPHA:
+		return V_028780_BLEND_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_ZERO:
+		return V_028780_BLEND_ZERO;
+	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_COLOR:
+		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_SRC1_COLOR:
+		return V_028780_BLEND_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_SRC1_ALPHA:
+		return V_028780_BLEND_SRC1_ALPHA;
+	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+		return V_028780_BLEND_INV_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+		return V_028780_BLEND_INV_SRC1_ALPHA;
+	default:
+		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static uint32_t r600_translate_stencil_op(int s_op)
+{
+	switch (s_op) {
+	case PIPE_STENCIL_OP_KEEP:
+		return V_028800_STENCIL_KEEP;
+	case PIPE_STENCIL_OP_ZERO:
+		return V_028800_STENCIL_ZERO;
+	case PIPE_STENCIL_OP_REPLACE:
+		return V_028800_STENCIL_REPLACE;
+	case PIPE_STENCIL_OP_INCR:
+		return V_028800_STENCIL_INCR;
+	case PIPE_STENCIL_OP_DECR:
+		return V_028800_STENCIL_DECR;
+	case PIPE_STENCIL_OP_INCR_WRAP:
+		return V_028800_STENCIL_INCR_WRAP;
+	case PIPE_STENCIL_OP_DECR_WRAP:
+		return V_028800_STENCIL_DECR_WRAP;
+	case PIPE_STENCIL_OP_INVERT:
+		return V_028800_STENCIL_INVERT;
+	default:
+		R600_ERR("Unknown stencil op %d", s_op);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static uint32_t r600_translate_fill(uint32_t func)
+{
+	switch(func) {
+	case PIPE_POLYGON_MODE_FILL:
+		return 2;
+	case PIPE_POLYGON_MODE_LINE:
+		return 1;
+	case PIPE_POLYGON_MODE_POINT:
+		return 0;
+	default:
+		assert(0);
+		return 0;
+	}
+}
+
+/* translates straight */
+static uint32_t r600_translate_ds_func(int func)
+{
+	return func;
+}
+
+static unsigned r600_tex_wrap(unsigned wrap)
+{
+	switch (wrap) {
+	default:
+	case PIPE_TEX_WRAP_REPEAT:
+		return V_03C000_SQ_TEX_WRAP;
+	case PIPE_TEX_WRAP_CLAMP:
+		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
+	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_CLAMP_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_REPEAT:
+		return V_03C000_SQ_TEX_MIRROR;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
+	}
+}
+
+static unsigned r600_tex_filter(unsigned filter)
+{
+	switch (filter) {
+	default:
+	case PIPE_TEX_FILTER_NEAREST:
+		return V_03C000_SQ_TEX_XY_FILTER_POINT;
+	case PIPE_TEX_FILTER_LINEAR:
+		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
+	}
+}
+
+static unsigned r600_tex_mipfilter(unsigned filter)
+{
+	switch (filter) {
+	case PIPE_TEX_MIPFILTER_NEAREST:
+		return V_03C000_SQ_TEX_Z_FILTER_POINT;
+	case PIPE_TEX_MIPFILTER_LINEAR:
+		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
+	default:
+	case PIPE_TEX_MIPFILTER_NONE:
+		return V_03C000_SQ_TEX_Z_FILTER_NONE;
+	}
+}
+
+static unsigned r600_tex_compare(unsigned compare)
+{
+	switch (compare) {
+	default:
+	case PIPE_FUNC_NEVER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
+	case PIPE_FUNC_LESS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
+	case PIPE_FUNC_EQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
+	case PIPE_FUNC_LEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+	case PIPE_FUNC_GREATER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
+	case PIPE_FUNC_NOTEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+	case PIPE_FUNC_GEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+	case PIPE_FUNC_ALWAYS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+	}
+}
+
+static unsigned r600_tex_dim(unsigned dim)
+{
+	switch (dim) {
+	default:
+	case PIPE_TEXTURE_1D:
+		return V_030000_SQ_TEX_DIM_1D;
+	case PIPE_TEXTURE_1D_ARRAY:
+		return V_030000_SQ_TEX_DIM_1D_ARRAY;
+	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
+		return V_030000_SQ_TEX_DIM_2D;
+	case PIPE_TEXTURE_2D_ARRAY:
+		return V_030000_SQ_TEX_DIM_2D_ARRAY;
+	case PIPE_TEXTURE_3D:
+		return V_030000_SQ_TEX_DIM_3D;
+	case PIPE_TEXTURE_CUBE:
+		return V_030000_SQ_TEX_DIM_CUBEMAP;
+	}
+}
+
+static uint32_t r600_translate_dbformat(enum pipe_format format)
+{
+	switch (format) {
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028040_Z_16;
+	case PIPE_FORMAT_Z24X8_UNORM:
+		return V_028040_Z_24;
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028040_Z_24;
+	default:
+		return ~0U;
+	}
+}
+
+static uint32_t r600_translate_stencilformat(enum pipe_format format)
+{
+	if (format == PIPE_FORMAT_Z24_UNORM_S8_USCALED)
+		return 1;
+	else
+		return 0;
+}
+
+static uint32_t r600_translate_colorswap(enum pipe_format format)
+{
+	switch (format) {
+	/* 8-bit buffers. */
+	case PIPE_FORMAT_L4A4_UNORM:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_A8_UNORM:
+		return V_028C70_SWAP_ALT_REV;
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_L8_SRGB:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_028C70_SWAP_STD;
+
+	/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_028C70_SWAP_STD_REV;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_L8A8_SRGB:
+		return V_028C70_SWAP_ALT;
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_R16_UNORM:
+	case PIPE_FORMAT_R16_FLOAT:
+		return V_028C70_SWAP_STD;
+
+	/* 32-bit buffers. */
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+		return V_028C70_SWAP_STD_REV;
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+		return V_028C70_SWAP_ALT_REV;
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
+		return V_028C70_SWAP_STD_REV;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_028C70_SWAP_STD;
+
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+		return V_028C70_SWAP_ALT;
+
+	case PIPE_FORMAT_R11G11B10_FLOAT:
+	case PIPE_FORMAT_R32_FLOAT:
+	case PIPE_FORMAT_R16G16_FLOAT:
+	case PIPE_FORMAT_R16G16_UNORM:
+		return V_028C70_SWAP_STD;
+
+	/* 64-bit buffers. */
+	case PIPE_FORMAT_R32G32_FLOAT:
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+
+	/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+	case PIPE_FORMAT_R32G32B32A32_SNORM:
+	case PIPE_FORMAT_R32G32B32A32_UNORM:
+		return V_028C70_SWAP_STD;
+	default:
+		R600_ERR("unsupported colorswap format %d\n", format);
+		return ~0U;
+	}
+	return ~0U;
+}
+
+static uint32_t r600_translate_colorformat(enum pipe_format format)
+{
+	switch (format) {
+	/* 8-bit buffers. */
+	case PIPE_FORMAT_L4A4_UNORM:
+		return V_028C70_COLOR_4_4;
+
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_L8_SRGB:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_028C70_COLOR_8;
+
+	/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_028C70_COLOR_5_6_5;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_028C70_COLOR_1_5_5_5;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_028C70_COLOR_4_4_4_4;
+
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028C70_COLOR_16;
+
+	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_L8A8_SRGB:
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_028C70_COLOR_8_8;
+
+	case PIPE_FORMAT_R16_UNORM:
+		return V_028C70_COLOR_16;
+
+	case PIPE_FORMAT_R16_FLOAT:
+		return V_028C70_COLOR_16_FLOAT;
+
+	/* 32-bit buffers. */
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+	case PIPE_FORMAT_R8G8B8_UNORM:
+		return V_028C70_COLOR_8_8_8_8;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_028C70_COLOR_2_10_10_10;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028C70_COLOR_8_24;
+
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_028C70_COLOR_24_8;
+
+	case PIPE_FORMAT_R32_FLOAT:
+		return V_028C70_COLOR_32_FLOAT;
+
+	case PIPE_FORMAT_R16G16_FLOAT:
+		return V_028C70_COLOR_16_16_FLOAT;
+
+	case PIPE_FORMAT_R16G16_SSCALED:
+	case PIPE_FORMAT_R16G16_UNORM:
+		return V_028C70_COLOR_16_16;
+
+	case PIPE_FORMAT_R11G11B10_FLOAT:
+		return V_028C70_COLOR_10_11_11_FLOAT;
+
+	/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16_USCALED:
+	case PIPE_FORMAT_R16G16B16A16_USCALED:
+	case PIPE_FORMAT_R16G16B16_SSCALED:
+	case PIPE_FORMAT_R16G16B16A16_SSCALED:
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+		return V_028C70_COLOR_16_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_FLOAT:
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		return V_028C70_COLOR_16_16_16_16_FLOAT;
+
+	case PIPE_FORMAT_R32G32_FLOAT:
+		return V_028C70_COLOR_32_32_FLOAT;
+
+	case PIPE_FORMAT_R32G32_USCALED:
+	case PIPE_FORMAT_R32G32_SSCALED:
+		return V_028C70_COLOR_32_32;
+
+	/* 96-bit buffers. */
+	case PIPE_FORMAT_R32G32B32_FLOAT:
+		return V_028C70_COLOR_32_32_32_FLOAT;
+
+	/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32A32_SNORM:
+	case PIPE_FORMAT_R32G32B32A32_UNORM:
+		return V_028C70_COLOR_32_32_32_32;
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		return V_028C70_COLOR_32_32_32_32_FLOAT;
+
+	/* YUV buffers. */
+	case PIPE_FORMAT_UYVY:
+	case PIPE_FORMAT_YUYV:
+	default:
+		return ~0U; /* Unsupported. */
+	}
+}
+
+static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
+{
+	if (R600_BIG_ENDIAN) {
+		switch(colorformat) {
+		case V_028C70_COLOR_4_4:
+			return ENDIAN_NONE;
+
+		/* 8-bit buffers. */
+		case V_028C70_COLOR_8:
+			return ENDIAN_NONE;
+
+		/* 16-bit buffers. */
+		case V_028C70_COLOR_5_6_5:
+		case V_028C70_COLOR_1_5_5_5:
+		case V_028C70_COLOR_4_4_4_4:
+		case V_028C70_COLOR_16:
+		case V_028C70_COLOR_8_8:
+			return ENDIAN_8IN16;
+
+		/* 32-bit buffers. */
+		case V_028C70_COLOR_8_8_8_8:
+		case V_028C70_COLOR_2_10_10_10:
+		case V_028C70_COLOR_8_24:
+		case V_028C70_COLOR_24_8:
+		case V_028C70_COLOR_32_FLOAT:
+		case V_028C70_COLOR_16_16_FLOAT:
+		case V_028C70_COLOR_16_16:
+			return ENDIAN_8IN32;
+
+		/* 64-bit buffers. */
+		case V_028C70_COLOR_16_16_16_16:
+		case V_028C70_COLOR_16_16_16_16_FLOAT:
+			return ENDIAN_8IN16;
+
+		case V_028C70_COLOR_32_32_FLOAT:
+		case V_028C70_COLOR_32_32:
+			return ENDIAN_8IN32;
+
+		/* 96-bit buffers. */
+		case V_028C70_COLOR_32_32_32_FLOAT:
+		/* 128-bit buffers. */
+		case V_028C70_COLOR_32_32_32_32_FLOAT:
+		case V_028C70_COLOR_32_32_32_32:
+			return ENDIAN_8IN32;
+		default:
+			return ENDIAN_NONE; /* Unsupported. */
+		}
+	} else {
+		return ENDIAN_NONE;
+	}
+}
+
+static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
+{
+	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
+}
+
+static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0U &&
+		r600_translate_colorswap(format) != ~0U;
+}
+
+static bool r600_is_zs_format_supported(enum pipe_format format)
+{
+	return r600_translate_dbformat(format) != ~0U;
+}
+
+boolean evergreen_is_format_supported(struct pipe_screen *screen,
+				      enum pipe_format format,
+				      enum pipe_texture_target target,
+				      unsigned sample_count,
+				      unsigned usage)
+{
+	unsigned retval = 0;
+
+	if (target >= PIPE_MAX_TEXTURE_TYPES) {
+		R600_ERR("r600: unsupported texture type %d\n", target);
+		return FALSE;
+	}
+
+	if (!util_format_is_supported(format, usage))
+		return FALSE;
+
+	/* Multisample */
+	if (sample_count > 1)
+		return FALSE;
+
+	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+	    r600_is_sampler_format_supported(screen, format)) {
+		retval |= PIPE_BIND_SAMPLER_VIEW;
+	}
+
+	if ((usage & (PIPE_BIND_RENDER_TARGET |
+		      PIPE_BIND_DISPLAY_TARGET |
+		      PIPE_BIND_SCANOUT |
+		      PIPE_BIND_SHARED)) &&
+	    r600_is_colorbuffer_format_supported(format)) {
+		retval |= usage &
+			  (PIPE_BIND_RENDER_TARGET |
+			   PIPE_BIND_DISPLAY_TARGET |
+			   PIPE_BIND_SCANOUT |
+			   PIPE_BIND_SHARED);
+	}
+
+	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+	    r600_is_zs_format_supported(format)) {
+		retval |= PIPE_BIND_DEPTH_STENCIL;
+	}
+
+	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+	    r600_is_vertex_format_supported(format)) {
+		retval |= PIPE_BIND_VERTEX_BUFFER;
+	}
+
+	if (usage & PIPE_BIND_TRANSFER_READ)
+		retval |= PIPE_BIND_TRANSFER_READ;
+	if (usage & PIPE_BIND_TRANSFER_WRITE)
+		retval |= PIPE_BIND_TRANSFER_WRITE;
+
+	return retval == usage;
+}
 
 static void evergreen_set_blend_color(struct pipe_context *ctx,
 					const struct pipe_blend_color *state)
@@ -77,13 +657,11 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
 	u32 color_control, target_mask;
 	/* FIXME there is more then 8 framebuffer */
 	unsigned blend_cntl[8];
-	enum radeon_family family;
 
 	if (blend == NULL) {
 		return NULL;
 	}
 
-	family = r600_get_family(rctx->radeon);
 	rstate = &blend->rstate;
 
 	rstate->id = R600_PIPE_STATE_BLEND;
@@ -110,7 +688,7 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
 	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 				color_control, 0xFFFFFFFD, NULL);
 
-	if (family != CHIP_CAYMAN)
+	if (rctx->chip_class != CAYMAN)
 		r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
 	else {
 		r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
@@ -247,9 +825,6 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
 	unsigned tmp;
 	unsigned prov_vtx = 1, polygon_dual_mode;
 	unsigned clip_rule;
-	enum radeon_family family;
-
-	family = r600_get_family(rctx->radeon);
 
 	if (rs == NULL) {
 		return NULL;
@@ -308,7 +883,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
 	tmp = (unsigned)state->line_width * 8;
 	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
 
-	if (family == CHIP_CAYMAN) {
+	if (rctx->chip_class == CAYMAN) {
 		r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
 					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
@@ -867,14 +1442,11 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 	u32 shader_mask, tl, br, target_mask;
-	enum radeon_family family;
 	int tl_x, tl_y, br_x, br_y;
 
 	if (rstate == NULL)
 		return;
 
-	family = r600_get_family(rctx->radeon);
-
 	evergreen_context_flush_dest_caches(&rctx->ctx);
 	rctx->ctx.num_dest_buffers = state->nr_cbufs;
 
@@ -911,7 +1483,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 	if (br_y == 0)
 		tl_y = 1;
 	/* cayman hw workaround */
-	if (family == CHIP_CAYMAN) {
+	if (rctx->chip_class == CAYMAN) {
 		if (br_x == 1 && br_y == 1)
 			br_x = 2;
 	}
@@ -955,7 +1527,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
 				shader_mask, 0xFFFFFFFF, NULL);
 
 
-	if (family == CHIP_CAYMAN) {
+	if (rctx->chip_class == CAYMAN) {
 		r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
 					0x00000000, 0xFFFFFFFF, NULL);
 	} else {
@@ -1142,9 +1714,9 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
 	enum radeon_family family;
 	unsigned tmp;
 
-	family = r600_get_family(rctx->radeon);
+	family = rctx->family;
 
-	if (family == CHIP_CAYMAN) {
+	if (rctx->chip_class == CAYMAN) {
 		cayman_init_config(rctx);
 		return;
 	}
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 151e831e5c6..2af4d311f60 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -228,6 +228,7 @@ struct r600_query {
 #define R600_QUERY_STATE_STARTED	(1 << 0)
 #define R600_QUERY_STATE_ENDED		(1 << 1)
 #define R600_QUERY_STATE_SUSPENDED	(1 << 2)
+#define R600_QUERY_STATE_FLUSHED	(1 << 3)
 
 #define R600_CONTEXT_DRAW_PENDING	(1 << 0)
 #define R600_CONTEXT_DST_CACHES_DIRTY	(1 << 1)
@@ -294,7 +295,7 @@ boolean r600_context_query_result(struct r600_context *ctx,
 void r600_query_begin(struct r600_context *ctx, struct r600_query *query);
 void r600_query_end(struct r600_context *ctx, struct r600_query *query);
 void r600_context_queries_suspend(struct r600_context *ctx);
-void r600_context_queries_resume(struct r600_context *ctx);
+void r600_context_queries_resume(struct r600_context *ctx, boolean flushed);
 void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
 			    int flag_wait);
 void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 065f955ebcb..5fae2b00c8b 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -41,9 +41,9 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r
 	if(alu->is_op3)
 		return 3;
 
-	switch (bc->chiprev) {
-	case CHIPREV_R600:
-	case CHIPREV_R700:
+	switch (bc->chip_class) {
+	case R600:
+	case R700:
 		switch (alu->inst) {
 		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
 			return 0;
@@ -93,8 +93,8 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r
 			"Need instruction operand number for 0x%x.\n", alu->inst);
 		}
 		break;
-	case CHIPREV_EVERGREEN:
-	case CHIPREV_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 		switch (alu->inst) {
 		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
 			return 0;
@@ -195,48 +195,10 @@ static struct r600_bc_tex *r600_bc_tex(void)
 	return tex;
 }
 
-int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
+void r600_bc_init(struct r600_bc *bc, enum chip_class chip_class)
 {
 	LIST_INITHEAD(&bc->cf);
-	bc->family = family;
-	switch (bc->family) {
-	case CHIP_R600:
-	case CHIP_RV610:
-	case CHIP_RV630:
-	case CHIP_RV670:
-	case CHIP_RV620:
-	case CHIP_RV635:
-	case CHIP_RS780:
-	case CHIP_RS880:
-		bc->chiprev = CHIPREV_R600;
-		break;
-	case CHIP_RV770:
-	case CHIP_RV730:
-	case CHIP_RV710:
-	case CHIP_RV740:
-		bc->chiprev = CHIPREV_R700;
-		break;
-	case CHIP_CEDAR:
-	case CHIP_REDWOOD:
-	case CHIP_JUNIPER:
-	case CHIP_CYPRESS:
-	case CHIP_HEMLOCK:
-	case CHIP_PALM:
-	case CHIP_SUMO:
-	case CHIP_SUMO2:
-	case CHIP_BARTS:
-	case CHIP_TURKS:
-	case CHIP_CAICOS:
-		bc->chiprev = CHIPREV_EVERGREEN;
-		break;
-	case CHIP_CAYMAN:
-		bc->chiprev = CHIPREV_CAYMAN;
-		break;
-	default:
-		R600_ERR("unknown family %d\n", bc->family);
-		return -EINVAL;
-	}
-	return 0;
+	bc->chip_class = chip_class;
 }
 
 static int r600_bc_add_cf(struct r600_bc *bc)
@@ -301,9 +263,9 @@ int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
 /* alu instructions that can ony exits once per group */
 static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
-	switch (bc->chiprev) {
-	case CHIPREV_R600:
-	case CHIPREV_R700:
+	switch (bc->chip_class) {
+	case R600:
+	case R700:
 		return !alu->is_op3 && (
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
@@ -339,8 +301,8 @@ static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
-	case CHIPREV_EVERGREEN:
-	case CHIPREV_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 	default:
 		return !alu->is_op3 && (
 			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
@@ -382,16 +344,16 @@ static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 
 static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
-	switch (bc->chiprev) {
-	case CHIPREV_R600:
-	case CHIPREV_R700:
+	switch (bc->chip_class) {
+	case R600:
+	case R700:
 		return !alu->is_op3 && (
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
-	case CHIPREV_EVERGREEN:
-	case CHIPREV_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 	default:
 		return !alu->is_op3 && (
 			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
@@ -403,13 +365,13 @@ static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 
 static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
-	switch (bc->chiprev) {
-	case CHIPREV_R600:
-	case CHIPREV_R700:
+	switch (bc->chip_class) {
+	case R600:
+	case R700:
 		return !alu->is_op3 &&
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
-	case CHIPREV_EVERGREEN:
-	case CHIPREV_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 	default:
 		return !alu->is_op3 &&
 			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
@@ -418,15 +380,15 @@ static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 
 static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
-	switch (bc->chiprev) {
-	case CHIPREV_R600:
-	case CHIPREV_R700:
+	switch (bc->chip_class) {
+	case R600:
+	case R700:
 		return !alu->is_op3 && (
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
 			alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
-	case CHIPREV_EVERGREEN:
-	case CHIPREV_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 	default:
 		return !alu->is_op3 && (
 			alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
@@ -438,16 +400,16 @@ static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
 	return is_alu_reduction_inst(bc, alu) ||
 		is_alu_mova_inst(bc, alu) ||
-		(bc->chiprev == CHIPREV_EVERGREEN &&
+		(bc->chip_class == EVERGREEN &&
 		alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR);
 }
 
 /* alu instructions that can only execute on the trans unit */
 static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 {
-	switch (bc->chiprev) {
-	case CHIPREV_R600:
-	case CHIPREV_R700:
+	switch (bc->chip_class) {
+	case R600:
+	case R700:
 		if (!alu->is_op3)
 			return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
 				alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
@@ -478,8 +440,8 @@ static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
 				alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
 				alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
 				alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
-	case CHIPREV_EVERGREEN:
-	case CHIPREV_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 	default:
 		if (!alu->is_op3)
 			/* Note that FLT_TO_INT_* instructions are vector-only instructions
@@ -525,7 +487,7 @@ static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
 {
 	struct r600_bc_alu *alu;
 	unsigned i, chan, trans;
-	int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+	int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
 
 	for (i = 0; i < max_slots; i++)
 		assignment[i] = NULL;
@@ -612,7 +574,7 @@ static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan,
 static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
 {
 	int res, num_res = 4;
-	if (bc->chiprev >= CHIPREV_R700) {
+	if (bc->chip_class >= R700) {
 		num_res = 2;
 		chan /= 2;
 	}
@@ -733,8 +695,8 @@ static int check_and_set_bank_swizzle(struct r600_bc *bc,
 	struct alu_bank_swizzle bs;
 	int bank_swizzle[5];
 	int i, r = 0, forced = 0;
-	boolean scalar_only = bc->chiprev == CHIPREV_CAYMAN ? false : true;
-	int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+	boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
+	int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
 
 	for (i = 0; i < max_slots; i++) {
 		if (slots[i] && slots[i]->bank_swizzle_force) {
@@ -806,7 +768,7 @@ static int replace_gpr_with_pv_ps(struct r600_bc *bc,
 	struct r600_bc_alu *prev[5];
 	int gpr[5], chan[5];
 	int i, j, r, src, num_src;
-	int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+	int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
 
 	r = assign_alu_units(bc, alu_prev, prev);
 	if (r)
@@ -834,7 +796,7 @@ static int replace_gpr_with_pv_ps(struct r600_bc *bc,
 			if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
 				continue;
 
-			if (bc->chiprev < CHIPREV_CAYMAN) {
+			if (bc->chip_class < CAYMAN) {
 				if (alu->src[src].sel == gpr[4] &&
 				    alu->src[src].chan == chan[4]) {
 					alu->src[src].sel = V_SQ_ALU_SRC_PS;
@@ -948,7 +910,7 @@ static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
 	int i, j, r, src, num_src;
 	int num_once_inst = 0;
 	int have_mova = 0, have_rel = 0;
-	int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+	int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
 
 	r = assign_alu_units(bc, alu_prev, prev);
 	if (r)
@@ -1252,7 +1214,7 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
 		uint32_t literal[4];
 		unsigned nliteral;
 		struct r600_bc_alu *slots[5];
-		int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+		int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
 		r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
 		if (r)
 			return r;
@@ -1302,26 +1264,26 @@ int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 
 static unsigned r600_bc_num_tex_and_vtx_instructions(const struct r600_bc *bc)
 {
-	switch (bc->chiprev) {
-	case CHIPREV_R600:
+	switch (bc->chip_class) {
+	case R600:
 		return 8;
 
-	case CHIPREV_R700:
+	case R700:
 		return 16;
 
-	case CHIPREV_EVERGREEN:
-	case CHIPREV_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 		return 64;
 
 	default:
-		R600_ERR("Unknown chiprev %d.\n", bc->chiprev);
+		R600_ERR("Unknown chip class %d.\n", bc->chip_class);
 		return 8;
 	}
 }
 
 static inline boolean last_inst_was_vtx_fetch(struct r600_bc *bc)
 {
-	if (bc->chiprev == CHIPREV_CAYMAN) {
+	if (bc->chip_class == CAYMAN) {
 		if (bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC)
 			return TRUE;
 	} else {
@@ -1350,7 +1312,7 @@ int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
 			free(nvtx);
 			return r;
 		}
-		if (bc->chiprev == CHIPREV_CAYMAN)
+		if (bc->chip_class == CAYMAN)
 			bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
 		else
 			bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
@@ -1438,7 +1400,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
 			S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
 			S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
 			S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
-	if (bc->chiprev < CHIPREV_CAYMAN)
+	if (bc->chip_class < CAYMAN)
 		bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
 	id++;
 	bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
@@ -1453,7 +1415,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
 				S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
 	bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
 				S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
-	if (bc->chiprev < CHIPREV_CAYMAN)
+	if (bc->chip_class < CAYMAN)
 		bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
 	id++;
 	bc->bytecode[id++] = 0;
@@ -1560,13 +1522,13 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 			S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
 			S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
 					S_SQ_CF_ALU_WORD1_BARRIER(1) |
-					S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
+					S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
 					S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
 		break;
 	case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
 	case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
 	case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
-		if (bc->chiprev == CHIPREV_R700)
+		if (bc->chip_class == R700)
 			r700_bc_cf_vtx_build(&bc->bytecode[id], cf);
 		else
 			r600_bc_cf_vtx_build(&bc->bytecode[id], cf);
@@ -1673,7 +1635,7 @@ int r600_bc_build(struct r600_bc *bc)
 		return -ENOMEM;
 	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
 		addr = cf->addr;
-		if (bc->chiprev >= CHIPREV_EVERGREEN)
+		if (bc->chip_class >= EVERGREEN)
 			r = eg_bc_cf_build(bc, cf);
 		else
 			r = r600_bc_cf_build(bc, cf);
@@ -1691,17 +1653,17 @@ int r600_bc_build(struct r600_bc *bc)
 				if (r)
 					return r;
 				r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
-				switch(bc->chiprev) {
-				case CHIPREV_R600:
+				switch(bc->chip_class) {
+				case R600:
 					r = r600_bc_alu_build(bc, alu, addr);
 					break;
-				case CHIPREV_R700:
-				case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
-				case CHIPREV_CAYMAN: /* eg alu is same encoding as r700 */
+				case R700:
+				case EVERGREEN: /* eg alu is same encoding as r700 */
+				case CAYMAN: /* eg alu is same encoding as r700 */
 					r = r700_bc_alu_build(bc, alu, addr);
 					break;
 				default:
-					R600_ERR("unknown family %d\n", bc->family);
+					R600_ERR("unknown chip class %d.\n", bc->chip_class);
 					return -EINVAL;
 				}
 				if (r)
@@ -1726,7 +1688,7 @@ int r600_bc_build(struct r600_bc *bc)
 			}
 			break;
 		case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
-			if (bc->chiprev == CHIPREV_CAYMAN) {
+			if (bc->chip_class == CAYMAN) {
 				LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
 					r = r600_bc_vtx_build(bc, vtx, addr);
 					if (r)
@@ -1812,17 +1774,17 @@ void r600_bc_dump(struct r600_bc *bc)
 	unsigned nliteral;
 	char chip = '6';
 
-	switch (bc->chiprev) {
-	case 1:
+	switch (bc->chip_class) {
+	case R700:
 		chip = '7';
 		break;
-	case 2:
+	case EVERGREEN:
 		chip = 'E';
 		break;
-	case 3:
+	case CAYMAN:
 		chip = 'C';
 		break;
-	case 0:
+	case R600:
 	default:
 		chip = '6';
 		break;
@@ -1993,7 +1955,7 @@ void r600_bc_dump(struct r600_bc *bc)
 			fprintf(stderr, "%04d %08X   ", id, bc->bytecode[id]);
 			fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
 			fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
-			if (bc->chiprev < CHIPREV_CAYMAN)
+			if (bc->chip_class < CAYMAN)
 				fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
 			else
 				fprintf(stderr, "SEL_Y:%d) ", 0);
@@ -2162,7 +2124,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 	struct r600_bc_vtx vtx;
 	struct pipe_vertex_element *elements = ve->elements;
 	const struct util_format_description *desc;
-	unsigned fetch_resource_start = rctx->family >= CHIP_CEDAR ? 0 : 160;
+	unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
 	unsigned format, num_format, format_comp, endian;
 	u32 *bytecode;
 	int i, r;
@@ -2180,9 +2142,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 	}
 
 	memset(&bc, 0, sizeof(bc));
-	r = r600_bc_init(&bc, r600_get_family(rctx->radeon));
-	if (r)
-		return r;
+	r600_bc_init(&bc, rctx->chip_class);
 
 	for (i = 0; i < ve->count; i++) {
 		if (elements[i].instance_divisor > 1) {
@@ -2287,7 +2247,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
 	r600_bo_unmap(rctx->radeon, ve->fetch_shader);
 	r600_bc_clear(&bc);
 
-	if (rctx->family >= CHIP_CEDAR)
+	if (rctx->chip_class >= EVERGREEN)
 		evergreen_fetch_shader(&rctx->context, ve);
 	else
 		r600_fetch_shader(&rctx->context, ve);
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 540f45bbd06..cbdaacf7178 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -171,8 +171,7 @@ struct r600_cf_callstack {
 };
 
 struct r600_bc {
-	enum radeon_family		family;
-	int				chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
+	enum chip_class			chip_class;
 	int				type;
 	struct list_head		cf;
 	struct r600_bc_cf		*cf_last;
@@ -193,7 +192,7 @@ struct r600_bc {
 int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf);
 
 /* r600_asm.c */
-int r600_bc_init(struct r600_bc *bc, enum radeon_family family);
+void r600_bc_init(struct r600_bc *bc, enum chip_class chip_class);
 void r600_bc_clear(struct r600_bc *bc);
 int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu);
 int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx);
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 6171d285bb9..35e68b6e222 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -97,7 +97,7 @@ static void r600_blitter_end(struct pipe_context *ctx)
 					       rctx->saved_render_cond_mode);
 		rctx->saved_render_cond = NULL;
 	}
-	r600_context_queries_resume(&rctx->ctx);
+	r600_context_queries_resume(&rctx->ctx, FALSE);
 	rctx->blit = false;
 }
 
diff --git a/src/gallium/drivers/r600/r600_formats.h b/src/gallium/drivers/r600/r600_formats.h
index ae0bc432ad2..1c1089d89d2 100644
--- a/src/gallium/drivers/r600/r600_formats.h
+++ b/src/gallium/drivers/r600/r600_formats.h
@@ -81,4 +81,36 @@ static INLINE unsigned r600_endian_swap(unsigned size)
 	}
 }
 
+static INLINE bool r600_is_vertex_format_supported(enum pipe_format format)
+{
+	const struct util_format_description *desc = util_format_description(format);
+	unsigned i;
+
+	if (!desc)
+		return false;
+
+	/* Find the first non-VOID channel. */
+	for (i = 0; i < 4; i++) {
+		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID)
+			break;
+	}
+	if (i == 4)
+		return false;
+
+	/* No fixed, no double. */
+	if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
+	    desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED ||
+	    (desc->channel[i].size == 64 &&
+	     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))
+		return false;
+
+	/* No scaled/norm formats with 32 bits per channel. */
+	if (desc->channel[i].size == 32 &&
+	    (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED ||
+	     desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED))
+		return false;
+
+	return true;
+}
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_opcodes.h b/src/gallium/drivers/r600/r600_opcodes.h
index 184f32c9960..7ae091ea5cd 100644
--- a/src/gallium/drivers/r600/r600_opcodes.h
+++ b/src/gallium/drivers/r600/r600_opcodes.h
@@ -409,14 +409,8 @@
 #define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT_COMBINED 0x0000005B
 #define     EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS  0x0000005C
 
+#define BC_INST(bc, x) ((bc)->chip_class >= EVERGREEN ? EG_##x : x)
 
-#define CHIPREV_R600      0
-#define CHIPREV_R700      1
-#define CHIPREV_EVERGREEN 2
-#define CHIPREV_CAYMAN    3
-
-#define BC_INST(bc, x) ((bc)->chiprev >= CHIPREV_EVERGREEN ? EG_##x : x)
-
-#define CTX_INST(x) (ctx->bc->chiprev >= CHIPREV_EVERGREEN ? EG_##x : x)
+#define CTX_INST(x) (ctx->bc->chip_class >= EVERGREEN ? EG_##x : x)
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 76bb1883ede..8e492787235 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -47,7 +47,6 @@
 #include "r600_resource.h"
 #include "r600_shader.h"
 #include "r600_pipe.h"
-#include "r600_state_inlines.h"
 
 /*
  * pipe_context
@@ -197,7 +196,6 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
 {
 	struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
 	struct r600_screen* rscreen = (struct r600_screen *)screen;
-	enum chip_class class;
 
 	if (rctx == NULL)
 		return NULL;
@@ -214,6 +212,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
 	rctx->screen = rscreen;
 	rctx->radeon = rscreen->radeon;
 	rctx->family = r600_get_family(rctx->radeon);
+	rctx->chip_class = r600_get_family_class(rctx->radeon);
 
 	rctx->fences.bo = NULL;
 	rctx->fences.data = NULL;
@@ -230,47 +229,29 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
 	rctx->context.create_video_decoder = vl_create_decoder;
 	rctx->context.create_video_buffer = vl_video_buffer_create;
 
-	switch (r600_get_family(rctx->radeon)) {
-	case CHIP_R600:
-	case CHIP_RV610:
-	case CHIP_RV630:
-	case CHIP_RV670:
-	case CHIP_RV620:
-	case CHIP_RV635:
-	case CHIP_RS780:
-	case CHIP_RS880:
-	case CHIP_RV770:
-	case CHIP_RV730:
-	case CHIP_RV710:
-	case CHIP_RV740:
+	switch (rctx->chip_class) {
+	case R600:
+	case R700:
 		r600_init_state_functions(rctx);
 		if (r600_context_init(&rctx->ctx, rctx->radeon)) {
 			r600_destroy_context(&rctx->context);
 			return NULL;
 		}
 		r600_init_config(rctx);
+		rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
 		break;
-	case CHIP_CEDAR:
-	case CHIP_REDWOOD:
-	case CHIP_JUNIPER:
-	case CHIP_CYPRESS:
-	case CHIP_HEMLOCK:
-	case CHIP_PALM:
-	case CHIP_SUMO:
-	case CHIP_SUMO2:
-	case CHIP_BARTS:
-	case CHIP_TURKS:
-	case CHIP_CAICOS:
-	case CHIP_CAYMAN:
+	case EVERGREEN:
+	case CAYMAN:
 		evergreen_init_state_functions(rctx);
 		if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
 			r600_destroy_context(&rctx->context);
 			return NULL;
 		}
 		evergreen_init_config(rctx);
+		rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
 		break;
 	default:
-		R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
+		R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
 		r600_destroy_context(&rctx->context);
 		return NULL;
 	}
@@ -295,12 +276,6 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
 		return NULL;
 	}
 
-	class = r600_get_family_class(rctx->radeon);
-	if (class == R600 || class == R700)
-		rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
-	else
-		rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
-
 	return &rctx->context;
 }
 
@@ -523,64 +498,6 @@ static int r600_get_video_param(struct pipe_screen *screen,
 	}
 }
 
-static boolean r600_is_format_supported(struct pipe_screen* screen,
-					enum pipe_format format,
-					enum pipe_texture_target target,
-					unsigned sample_count,
-                                        unsigned usage)
-{
-	unsigned retval = 0;
-	if (target >= PIPE_MAX_TEXTURE_TYPES) {
-		R600_ERR("r600: unsupported texture type %d\n", target);
-		return FALSE;
-	}
-
-        if (!util_format_is_supported(format, usage))
-                return FALSE;
-
-	/* Multisample */
-	if (sample_count > 1)
-		return FALSE;
-
-	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
-	    r600_is_sampler_format_supported(screen, format)) {
-		retval |= PIPE_BIND_SAMPLER_VIEW;
-	}
-
-	if ((usage & (PIPE_BIND_RENDER_TARGET |
-			PIPE_BIND_DISPLAY_TARGET |
-			PIPE_BIND_SCANOUT |
-			PIPE_BIND_SHARED)) &&
-			r600_is_colorbuffer_format_supported(format)) {
-		retval |= usage &
-			(PIPE_BIND_RENDER_TARGET |
-			 PIPE_BIND_DISPLAY_TARGET |
-			 PIPE_BIND_SCANOUT |
-			 PIPE_BIND_SHARED);
-	}
-
-	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
-	    r600_is_zs_format_supported(format)) {
-		retval |= PIPE_BIND_DEPTH_STENCIL;
-	}
-
-	if (usage & PIPE_BIND_VERTEX_BUFFER) {
-		struct r600_screen *rscreen = (struct r600_screen *)screen;
-		enum radeon_family family = r600_get_family(rscreen->radeon);
-
-		if (r600_is_vertex_format_supported(format, family)) {
-			retval |= PIPE_BIND_VERTEX_BUFFER;
-		}
-	}
-
-	if (usage & PIPE_BIND_TRANSFER_READ)
-		retval |= PIPE_BIND_TRANSFER_READ;
-	if (usage & PIPE_BIND_TRANSFER_WRITE)
-		retval |= PIPE_BIND_TRANSFER_WRITE;
-
-	return retval == usage;
-}
-
 static void r600_destroy_screen(struct pipe_screen* pscreen)
 {
 	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
@@ -670,7 +587,11 @@ struct pipe_screen *r600_screen_create(struct radeon *radeon)
 	rscreen->screen.get_shader_param = r600_get_shader_param;
 	rscreen->screen.get_paramf = r600_get_paramf;
 	rscreen->screen.get_video_param = r600_get_video_param;
-	rscreen->screen.is_format_supported = r600_is_format_supported;
+	if (r600_get_family_class(radeon) >= EVERGREEN) {
+		rscreen->screen.is_format_supported = evergreen_is_format_supported;
+	} else {
+		rscreen->screen.is_format_supported = r600_is_format_supported;
+	}
 	rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
 	rscreen->screen.context_create = r600_create_context;
 	rscreen->screen.fence_reference = r600_fence_reference;
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 2667c80bcef..6f399ed43b0 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -175,7 +175,8 @@ struct r600_pipe_fences {
 struct r600_pipe_context {
 	struct pipe_context		context;
 	struct blitter_context		*blitter;
-	unsigned			family;
+	enum radeon_family		family;
+	enum chip_class			chip_class;
 	void				*custom_dsa_flush;
 	struct r600_screen		*screen;
 	struct radeon			*radeon;
@@ -247,6 +248,11 @@ void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 					struct r600_resource *rbuffer,
 					unsigned offset, unsigned stride);
+boolean evergreen_is_format_supported(struct pipe_screen *screen,
+				      enum pipe_format format,
+				      enum pipe_texture_target target,
+				      unsigned sample_count,
+				      unsigned usage);
 
 /* r600_blit.c */
 void r600_init_blit_functions(struct r600_pipe_context *rctx);
@@ -290,6 +296,11 @@ void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 				   struct r600_resource *rbuffer,
 				   unsigned offset, unsigned stride);
 void r600_adjust_gprs(struct r600_pipe_context *rctx);
+boolean r600_is_format_supported(struct pipe_screen *screen,
+				 enum pipe_format format,
+				 enum pipe_texture_target target,
+				 unsigned sample_count,
+				 unsigned usage);
 
 /* r600_texture.c */
 void r600_init_screen_texture_functions(struct pipe_screen *screen);
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index bedb48b6031..174505c75e9 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -61,10 +61,7 @@ static boolean r600_get_query_result(struct pipe_context *ctx,
 	struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 	struct r600_query *rquery = (struct r600_query *)query;
 
-	if (rquery->num_results) {
-                ctx->flush(ctx, NULL);
-	}
-	return r600_context_query_result(&rctx->ctx, (struct r600_query *)query, wait, vresult);
+	return r600_context_query_result(&rctx->ctx, rquery, wait, vresult);
 }
 
 static void r600_render_condition(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index f83d7079b29..3e21ad1fdc6 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -99,14 +99,14 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *s
 	/* build state */
 	switch (rshader->processor_type) {
 	case TGSI_PROCESSOR_VERTEX:
-		if (rshader->family >= CHIP_CEDAR) {
+		if (rctx->chip_class >= EVERGREEN) {
 			evergreen_pipe_shader_vs(ctx, shader);
 		} else {
 			r600_pipe_shader_vs(ctx, shader);
 		}
 		break;
 	case TGSI_PROCESSOR_FRAGMENT:
-		if (rshader->family >= CHIP_CEDAR) {
+		if (rctx->chip_class >= EVERGREEN) {
 			evergreen_pipe_shader_ps(ctx, shader);
 		} else {
 			r600_pipe_shader_ps(ctx, shader);
@@ -135,7 +135,6 @@ int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *s
 		fprintf(stderr, "--------------------------------------------------------------\n");
 		tgsi_dump(shader->tokens, 0);
 	}
-	shader->shader.family = r600_get_family(rctx->radeon);
 	r = r600_shader_from_tgsi(rctx, shader);
 	if (r) {
 		R600_ERR("translation from TGSI failed !\n");
@@ -317,7 +316,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 		ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
 		ctx->shader->input[i].centroid = d->Declaration.Centroid;
 		ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
-		if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev >= CHIPREV_EVERGREEN) {
+		if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chip_class >= EVERGREEN) {
 			/* turn input into interpolate on EG */
 			if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
 				if (ctx->shader->input[i].interpolate > 0) {
@@ -610,9 +609,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
 
 	ctx.bc = &shader->bc;
 	ctx.shader = shader;
-	r = r600_bc_init(ctx.bc, shader->family);
-	if (r)
-		return r;
+	r600_bc_init(ctx.bc, rctx->chip_class);
 	ctx.tokens = tokens;
 	tgsi_scan_shader(tokens, &ctx.info);
 	tgsi_parse_init(&ctx.parse, tokens);
@@ -651,13 +648,13 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
 	}
 	if (ctx.type == TGSI_PROCESSOR_VERTEX) {
 		ctx.file_offset[TGSI_FILE_INPUT] = 1;
-		if (ctx.bc->chiprev >= CHIPREV_EVERGREEN) {
+		if (ctx.bc->chip_class >= EVERGREEN) {
 			r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
 		} else {
 			r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
 		}
 	}
-	if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev >= CHIPREV_EVERGREEN) {
+	if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
 		ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
 	}
 	ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
@@ -711,9 +708,9 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
 				goto out_err;
 			if ((r = tgsi_split_literal_constant(&ctx)))
 				goto out_err;
-			if (ctx.bc->chiprev == CHIPREV_CAYMAN)
+			if (ctx.bc->chip_class == CAYMAN)
 				ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
-			else if (ctx.bc->chiprev >= CHIPREV_EVERGREEN)
+			else if (ctx.bc->chip_class >= EVERGREEN)
 				ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
 			else
 				ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
@@ -802,7 +799,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
 			if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
 				output[i + j].array_base = shader->output[i].sid;
 				output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
-				if (shader->fs_write_all && (shader->family >= CHIP_CEDAR)) {
+				if (shader->fs_write_all && (rctx->chip_class >= EVERGREEN)) {
 					for (j = 1; j < shader->nr_cbufs; j++) {
 						memset(&output[i + j], 0, sizeof(struct r600_bc_output));
 						output[i + j].gpr = shader->output[i].gpr;
@@ -886,7 +883,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
 	}
 	/* set export done on last export of each type */
 	for (i = noutput - 1, output_done = 0; i >= 0; i--) {
-		if (ctx.bc->chiprev < CHIPREV_CAYMAN) {
+		if (ctx.bc->chip_class < CAYMAN) {
 			if (i == (noutput - 1)) {
 				output[i].end_of_program = 1;
 			}
@@ -903,7 +900,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
 			goto out_err;
 	}
 	/* add program end */
-	if (ctx.bc->chiprev == CHIPREV_CAYMAN)
+	if (ctx.bc->chip_class == CAYMAN)
 		cm_bc_add_cf_end(ctx.bc);
 
 	free(ctx.literals);
@@ -939,6 +936,17 @@ static void r600_bc_src(struct r600_bc_alu_src *bc_src,
 	bc_src->value = shader_src->value[bc_src->chan];
 }
 
+static void r600_bc_src_set_abs(struct r600_bc_alu_src *bc_src)
+{
+	bc_src->abs = 1;
+	bc_src->neg = 0;
+}
+
+static void r600_bc_src_toggle_neg(struct r600_bc_alu_src *bc_src)
+{
+	bc_src->neg = !bc_src->neg;
+}
+
 static void tgsi_dst(struct r600_shader_ctx *ctx,
 		     const struct tgsi_full_dst_register *tgsi_dst,
 		     unsigned swizzle,
@@ -995,12 +1003,10 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
 		/* handle some special cases */
 		switch (ctx->inst_info->tgsi_opcode) {
 		case TGSI_OPCODE_SUB:
-			alu.src[1].neg = 1;
+			r600_bc_src_toggle_neg(&alu.src[1]);
 			break;
 		case TGSI_OPCODE_ABS:
-			alu.src[0].abs = 1;
-			if (alu.src[0].neg)
-			  alu.src[0].neg = 0;
+			r600_bc_src_set_abs(&alu.src[0]);
 			break;
 		default:
 			break;
@@ -1114,7 +1120,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
 	alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
 	alu.src[2].chan = 0;
 
-	if (ctx->bc->chiprev == CHIPREV_R600) {
+	if (ctx->bc->chip_class == R600) {
 		alu.src[1].value = *(uint32_t *)&double_pi;
 		alu.src[2].value = *(uint32_t *)&neg_pi;
 	} else {
@@ -1221,7 +1227,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 
 	/* dst.x = COS */
 	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0 ; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
@@ -1255,7 +1261,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 
 	/* dst.y = SIN */
 	if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0 ; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
@@ -1364,19 +1370,37 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	struct r600_bc_alu alu;
 	int r;
 
+	/* tmp.x = max(src.y, 0.0) */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
+	r600_bc_src(&alu.src[0], &ctx->src[0], 1);
+	alu.src[1].sel  = V_SQ_ALU_SRC_0; /*0.0*/
+	alu.src[1].chan = 1;
+
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 0;
+	alu.dst.write = 1;
+
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+
 	if (inst->Dst[0].Register.WriteMask & (1 << 2))
 	{
 		int chan;
 		int sel;
 		int i;
 
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
-				/* dst.z = log(src.y) */
+				/* tmp.z = log(tmp.x) */
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
-				r600_bc_src(&alu.src[0], &ctx->src[0], 1);
-				tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+				alu.src[0].sel = ctx->temp_reg;
+				alu.src[0].chan = 0;
+				alu.dst.sel = ctx->temp_reg;
+				alu.dst.chan = i;
 				if (i == 2) {
 					alu.dst.write = 1;
 					alu.last = 1;
@@ -1388,10 +1412,11 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 					return r;
 			}
 		} else {
-			/* dst.z = log(src.y) */
+			/* tmp.z = log(tmp.x) */
 			memset(&alu, 0, sizeof(struct r600_bc_alu));
 			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
-			r600_bc_src(&alu.src[0], &ctx->src[0], 1);
+			alu.src[0].sel = ctx->temp_reg;
+			alu.src[0].chan = 0;
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.chan = 2;
 			alu.dst.write = 1;
@@ -1404,13 +1429,12 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		chan = alu.dst.chan;
 		sel = alu.dst.sel;
 
-		/* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
+		/* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
-		r600_bc_src(&alu.src[0], &ctx->src[0], 3);
-		alu.src[1].sel  = sel;
-		alu.src[1].chan = chan;
-
+		alu.src[0].sel  = sel;
+		alu.src[0].chan = chan;
+		r600_bc_src(&alu.src[1], &ctx->src[0], 3);
 		r600_bc_src(&alu.src[2], &ctx->src[0], 0);
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = 0;
@@ -1421,7 +1445,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				/* dst.z = exp(tmp.x) */
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -1506,7 +1530,7 @@ static int tgsi_rsq(struct r600_shader_ctx *ctx)
 
 	for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
 		r600_bc_src(&alu.src[i], &ctx->src[i], 0);
-		alu.src[i].abs = 1;
+		r600_bc_src_set_abs(&alu.src[i]);
 	}
 	alu.dst.sel = ctx->temp_reg;
 	alu.dst.write = 1;
@@ -1898,7 +1922,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	} else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
 		int out_chan;
 		/* Add perspective divide */
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			out_chan = 2;
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -1980,7 +2004,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		}
 
 		/* tmp1.z = RCP_e(|tmp1.z|) */
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
@@ -2192,7 +2216,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 		alu.src[0].sel = V_SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 		r600_bc_src(&alu.src[1], &ctx->src[0], i);
-		alu.src[1].neg = 1;
+		r600_bc_src_toggle_neg(&alu.src[1]);
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = i;
 		if (i == lasti) {
@@ -2373,7 +2397,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
 				alu.src[0].sel = ctx->temp_reg;
@@ -2429,7 +2453,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 
 	/* result.z = RoughApprox2ToX(tmp);*/
 	if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
@@ -2489,14 +2513,15 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 	int r;
 	int i;
 
-	/* result.x = floor(log2(src)); */
+	/* result.x = floor(log2(|src|)); */
 	if (inst->Dst[0].Register.WriteMask & 1) {
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
 				r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+				r600_bc_src_set_abs(&alu.src[0]);
 			
 				alu.dst.sel = ctx->temp_reg;
 				alu.dst.chan = i;
@@ -2514,6 +2539,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 
 			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
 			r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+			r600_bc_src_set_abs(&alu.src[0]);
 			
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.chan = 0;
@@ -2538,15 +2564,16 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 			return r;
 	}
 
-	/* result.y = src.x / (2 ^ floor(log2(src.x))); */
+	/* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
 	if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
 
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
 				r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+				r600_bc_src_set_abs(&alu.src[0]);
 
 				alu.dst.sel = ctx->temp_reg;
 				alu.dst.chan = i;
@@ -2564,6 +2591,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 
 			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
 			r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+			r600_bc_src_set_abs(&alu.src[0]);
 
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.chan = 1;
@@ -2590,7 +2618,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
@@ -2624,7 +2652,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 				return r;
 		}
 
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
@@ -2663,6 +2691,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 		alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
 
 		r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+		r600_bc_src_set_abs(&alu.src[0]);
 
 		alu.src[1].sel = ctx->temp_reg;
 		alu.src[1].chan = 1;
@@ -2677,14 +2706,15 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 			return r;
 	}
 
-	/* result.z = log2(src);*/
+	/* result.z = log2(|src|);*/
 	if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
-		if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+		if (ctx->bc->chip_class == CAYMAN) {
 			for (i = 0; i < 3; i++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 
 				alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
 				r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+				r600_bc_src_set_abs(&alu.src[0]);
 
 				alu.dst.sel = ctx->temp_reg;
 				if (i == 2)
@@ -2702,6 +2732,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
 
 			alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
 			r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+			r600_bc_src_set_abs(&alu.src[0]);
 
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.write = 1;
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index 76aebf2b1ea..3ba84bd8907 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -43,7 +43,6 @@ struct r600_shader {
 	unsigned		nlds;
 	struct r600_shader_io	input[32];
 	struct r600_shader_io	output[32];
-	enum radeon_family	family;
 	boolean			uses_kill;
 	boolean			fs_write_all;
 	boolean			clamp_color;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 7c1976f12e0..f8f7c2031db 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -44,7 +44,590 @@
 #include "r600_resource.h"
 #include "r600_shader.h"
 #include "r600_pipe.h"
-#include "r600_state_inlines.h"
+#include "r600_formats.h"
+
+static uint32_t r600_translate_blend_function(int blend_func)
+{
+	switch (blend_func) {
+	case PIPE_BLEND_ADD:
+		return V_028804_COMB_DST_PLUS_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return V_028804_COMB_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return V_028804_COMB_DST_MINUS_SRC;
+	case PIPE_BLEND_MIN:
+		return V_028804_COMB_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return V_028804_COMB_MAX_DST_SRC;
+	default:
+		R600_ERR("Unknown blend function %d\n", blend_func);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static uint32_t r600_translate_blend_factor(int blend_fact)
+{
+	switch (blend_fact) {
+	case PIPE_BLENDFACTOR_ONE:
+		return V_028804_BLEND_ONE;
+	case PIPE_BLENDFACTOR_SRC_COLOR:
+		return V_028804_BLEND_SRC_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA:
+		return V_028804_BLEND_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_DST_ALPHA:
+		return V_028804_BLEND_DST_ALPHA;
+	case PIPE_BLENDFACTOR_DST_COLOR:
+		return V_028804_BLEND_DST_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+		return V_028804_BLEND_SRC_ALPHA_SATURATE;
+	case PIPE_BLENDFACTOR_CONST_COLOR:
+		return V_028804_BLEND_CONST_COLOR;
+	case PIPE_BLENDFACTOR_CONST_ALPHA:
+		return V_028804_BLEND_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_ZERO:
+		return V_028804_BLEND_ZERO;
+	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_COLOR:
+		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_SRC1_COLOR:
+		return V_028804_BLEND_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_SRC1_ALPHA:
+		return V_028804_BLEND_SRC1_ALPHA;
+	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+		return V_028804_BLEND_INV_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+		return V_028804_BLEND_INV_SRC1_ALPHA;
+	default:
+		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static uint32_t r600_translate_stencil_op(int s_op)
+{
+	switch (s_op) {
+	case PIPE_STENCIL_OP_KEEP:
+		return V_028800_STENCIL_KEEP;
+	case PIPE_STENCIL_OP_ZERO:
+		return V_028800_STENCIL_ZERO;
+	case PIPE_STENCIL_OP_REPLACE:
+		return V_028800_STENCIL_REPLACE;
+	case PIPE_STENCIL_OP_INCR:
+		return V_028800_STENCIL_INCR;
+	case PIPE_STENCIL_OP_DECR:
+		return V_028800_STENCIL_DECR;
+	case PIPE_STENCIL_OP_INCR_WRAP:
+		return V_028800_STENCIL_INCR_WRAP;
+	case PIPE_STENCIL_OP_DECR_WRAP:
+		return V_028800_STENCIL_DECR_WRAP;
+	case PIPE_STENCIL_OP_INVERT:
+		return V_028800_STENCIL_INVERT;
+	default:
+		R600_ERR("Unknown stencil op %d", s_op);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+static uint32_t r600_translate_fill(uint32_t func)
+{
+	switch(func) {
+	case PIPE_POLYGON_MODE_FILL:
+		return 2;
+	case PIPE_POLYGON_MODE_LINE:
+		return 1;
+	case PIPE_POLYGON_MODE_POINT:
+		return 0;
+	default:
+		assert(0);
+		return 0;
+	}
+}
+
+/* translates straight */
+static uint32_t r600_translate_ds_func(int func)
+{
+	return func;
+}
+
+static unsigned r600_tex_wrap(unsigned wrap)
+{
+	switch (wrap) {
+	default:
+	case PIPE_TEX_WRAP_REPEAT:
+		return V_03C000_SQ_TEX_WRAP;
+	case PIPE_TEX_WRAP_CLAMP:
+		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
+	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_CLAMP_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_REPEAT:
+		return V_03C000_SQ_TEX_MIRROR;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
+	}
+}
+
+static unsigned r600_tex_filter(unsigned filter)
+{
+	switch (filter) {
+	default:
+	case PIPE_TEX_FILTER_NEAREST:
+		return V_03C000_SQ_TEX_XY_FILTER_POINT;
+	case PIPE_TEX_FILTER_LINEAR:
+		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
+	}
+}
+
+static unsigned r600_tex_mipfilter(unsigned filter)
+{
+	switch (filter) {
+	case PIPE_TEX_MIPFILTER_NEAREST:
+		return V_03C000_SQ_TEX_Z_FILTER_POINT;
+	case PIPE_TEX_MIPFILTER_LINEAR:
+		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
+	default:
+	case PIPE_TEX_MIPFILTER_NONE:
+		return V_03C000_SQ_TEX_Z_FILTER_NONE;
+	}
+}
+
+static unsigned r600_tex_compare(unsigned compare)
+{
+	switch (compare) {
+	default:
+	case PIPE_FUNC_NEVER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
+	case PIPE_FUNC_LESS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
+	case PIPE_FUNC_EQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
+	case PIPE_FUNC_LEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+	case PIPE_FUNC_GREATER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
+	case PIPE_FUNC_NOTEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+	case PIPE_FUNC_GEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+	case PIPE_FUNC_ALWAYS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+	}
+}
+
+static unsigned r600_tex_dim(unsigned dim)
+{
+	switch (dim) {
+	default:
+	case PIPE_TEXTURE_1D:
+		return V_038000_SQ_TEX_DIM_1D;
+	case PIPE_TEXTURE_1D_ARRAY:
+		return V_038000_SQ_TEX_DIM_1D_ARRAY;
+	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
+		return V_038000_SQ_TEX_DIM_2D;
+	case PIPE_TEXTURE_2D_ARRAY:
+		return V_038000_SQ_TEX_DIM_2D_ARRAY;
+	case PIPE_TEXTURE_3D:
+		return V_038000_SQ_TEX_DIM_3D;
+	case PIPE_TEXTURE_CUBE:
+		return V_038000_SQ_TEX_DIM_CUBEMAP;
+	}
+}
+
+static uint32_t r600_translate_dbformat(enum pipe_format format)
+{
+	switch (format) {
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028010_DEPTH_16;
+	case PIPE_FORMAT_Z24X8_UNORM:
+		return V_028010_DEPTH_X8_24;
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028010_DEPTH_8_24;
+	case PIPE_FORMAT_Z32_FLOAT:
+		return V_028010_DEPTH_32_FLOAT;
+	case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+		return V_028010_DEPTH_X24_8_32_FLOAT;
+	default:
+		return ~0U;
+	}
+}
+
+static uint32_t r600_translate_colorswap(enum pipe_format format)
+{
+	switch (format) {
+	/* 8-bit buffers. */
+	case PIPE_FORMAT_A8_UNORM:
+		return V_0280A0_SWAP_ALT_REV;
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_L8_SRGB:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_L4A4_UNORM:
+		return V_0280A0_SWAP_ALT;
+
+	/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_0280A0_SWAP_STD_REV;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_L8A8_SRGB:
+		return V_0280A0_SWAP_ALT;
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_R16_UNORM:
+	case PIPE_FORMAT_R16_FLOAT:
+		return V_0280A0_SWAP_STD;
+
+	/* 32-bit buffers. */
+
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+		return V_0280A0_SWAP_STD_REV;
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+		return V_0280A0_SWAP_ALT_REV;
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
+		return V_0280A0_SWAP_STD_REV;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_0280A0_SWAP_STD;
+
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+		return V_0280A0_SWAP_ALT;
+
+	case PIPE_FORMAT_R11G11B10_FLOAT:
+	case PIPE_FORMAT_R16G16_UNORM:
+	case PIPE_FORMAT_R16G16_FLOAT:
+	case PIPE_FORMAT_R32_FLOAT:
+	case PIPE_FORMAT_Z32_FLOAT:
+		return V_0280A0_SWAP_STD;
+
+	/* 64-bit buffers. */
+	case PIPE_FORMAT_R32G32_FLOAT:
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+	case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+
+	/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+	case PIPE_FORMAT_R32G32B32A32_SNORM:
+	case PIPE_FORMAT_R32G32B32A32_UNORM:
+		return V_0280A0_SWAP_STD;
+	default:
+		R600_ERR("unsupported colorswap format %d\n", format);
+		return ~0U;
+	}
+	return ~0U;
+}
+
+static uint32_t r600_translate_colorformat(enum pipe_format format)
+{
+	switch (format) {
+	case PIPE_FORMAT_L4A4_UNORM:
+		return V_0280A0_COLOR_4_4;
+
+	/* 8-bit buffers. */
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_L8_SRGB:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_0280A0_COLOR_8;
+
+	/* 16-bit buffers. */
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_0280A0_COLOR_5_6_5;
+
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_0280A0_COLOR_1_5_5_5;
+
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_0280A0_COLOR_4_4_4_4;
+
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_0280A0_COLOR_16;
+
+	case PIPE_FORMAT_L8A8_UNORM:
+	case PIPE_FORMAT_L8A8_SRGB:
+	case PIPE_FORMAT_R8G8_UNORM:
+		return V_0280A0_COLOR_8_8;
+
+	case PIPE_FORMAT_R16_UNORM:
+		return V_0280A0_COLOR_16;
+
+	case PIPE_FORMAT_R16_FLOAT:
+		return V_0280A0_COLOR_16_FLOAT;
+
+	/* 32-bit buffers. */
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+	case PIPE_FORMAT_R8G8B8_UNORM:
+		return V_0280A0_COLOR_8_8_8_8;
+
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_0280A0_COLOR_2_10_10_10;
+
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_0280A0_COLOR_8_24;
+
+	case PIPE_FORMAT_X8Z24_UNORM:
+	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		return V_0280A0_COLOR_24_8;
+
+	case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+		return V_0280A0_COLOR_X24_8_32_FLOAT;
+
+	case PIPE_FORMAT_R32_FLOAT:
+	case PIPE_FORMAT_Z32_FLOAT:
+		return V_0280A0_COLOR_32_FLOAT;
+
+	case PIPE_FORMAT_R16G16_FLOAT:
+		return V_0280A0_COLOR_16_16_FLOAT;
+
+	case PIPE_FORMAT_R16G16_SSCALED:
+	case PIPE_FORMAT_R16G16_UNORM:
+		return V_0280A0_COLOR_16_16;
+
+	case PIPE_FORMAT_R11G11B10_FLOAT:
+		return V_0280A0_COLOR_10_11_11_FLOAT;
+
+	/* 64-bit buffers. */
+	case PIPE_FORMAT_R16G16B16_USCALED:
+	case PIPE_FORMAT_R16G16B16A16_USCALED:
+	case PIPE_FORMAT_R16G16B16_SSCALED:
+	case PIPE_FORMAT_R16G16B16A16_SSCALED:
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+		return V_0280A0_COLOR_16_16_16_16;
+
+	case PIPE_FORMAT_R16G16B16_FLOAT:
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+
+	case PIPE_FORMAT_R32G32_FLOAT:
+		return V_0280A0_COLOR_32_32_FLOAT;
+
+	case PIPE_FORMAT_R32G32_USCALED:
+	case PIPE_FORMAT_R32G32_SSCALED:
+		return V_0280A0_COLOR_32_32;
+
+	/* 96-bit buffers. */
+	case PIPE_FORMAT_R32G32B32_FLOAT:
+		return V_0280A0_COLOR_32_32_32_FLOAT;
+
+	/* 128-bit buffers. */
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		return V_0280A0_COLOR_32_32_32_32_FLOAT;
+	case PIPE_FORMAT_R32G32B32A32_SNORM:
+	case PIPE_FORMAT_R32G32B32A32_UNORM:
+		return V_0280A0_COLOR_32_32_32_32;
+
+	/* YUV buffers. */
+	case PIPE_FORMAT_UYVY:
+	case PIPE_FORMAT_YUYV:
+	default:
+		return ~0U; /* Unsupported. */
+	}
+}
+
+static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
+{
+	if (R600_BIG_ENDIAN) {
+		switch(colorformat) {
+		case V_0280A0_COLOR_4_4:
+			return ENDIAN_NONE;
+
+		/* 8-bit buffers. */
+		case V_0280A0_COLOR_8:
+			return ENDIAN_NONE;
+
+		/* 16-bit buffers. */
+		case V_0280A0_COLOR_5_6_5:
+		case V_0280A0_COLOR_1_5_5_5:
+		case V_0280A0_COLOR_4_4_4_4:
+		case V_0280A0_COLOR_16:
+		case V_0280A0_COLOR_8_8:
+			return ENDIAN_8IN16;
+
+		/* 32-bit buffers. */
+		case V_0280A0_COLOR_8_8_8_8:
+		case V_0280A0_COLOR_2_10_10_10:
+		case V_0280A0_COLOR_8_24:
+		case V_0280A0_COLOR_24_8:
+		case V_0280A0_COLOR_32_FLOAT:
+		case V_0280A0_COLOR_16_16_FLOAT:
+		case V_0280A0_COLOR_16_16:
+			return ENDIAN_8IN32;
+
+		/* 64-bit buffers. */
+		case V_0280A0_COLOR_16_16_16_16:
+		case V_0280A0_COLOR_16_16_16_16_FLOAT:
+			return ENDIAN_8IN16;
+
+		case V_0280A0_COLOR_32_32_FLOAT:
+		case V_0280A0_COLOR_32_32:
+		case V_0280A0_COLOR_X24_8_32_FLOAT:
+			return ENDIAN_8IN32;
+
+		/* 128-bit buffers. */
+		case V_0280A0_COLOR_32_32_32_FLOAT:
+		case V_0280A0_COLOR_32_32_32_32_FLOAT:
+		case V_0280A0_COLOR_32_32_32_32:
+			return ENDIAN_8IN32;
+		default:
+			return ENDIAN_NONE; /* Unsupported. */
+		}
+	} else {
+		return ENDIAN_NONE;
+	}
+}
+
+static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
+{
+	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
+}
+
+static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0U &&
+	       r600_translate_colorswap(format) != ~0U;
+}
+
+static bool r600_is_zs_format_supported(enum pipe_format format)
+{
+	return r600_translate_dbformat(format) != ~0U;
+}
+
+boolean r600_is_format_supported(struct pipe_screen *screen,
+				 enum pipe_format format,
+				 enum pipe_texture_target target,
+				 unsigned sample_count,
+				 unsigned usage)
+{
+	unsigned retval = 0;
+
+	if (target >= PIPE_MAX_TEXTURE_TYPES) {
+		R600_ERR("r600: unsupported texture type %d\n", target);
+		return FALSE;
+	}
+
+	if (!util_format_is_supported(format, usage))
+		return FALSE;
+
+	/* Multisample */
+	if (sample_count > 1)
+		return FALSE;
+
+	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+	    r600_is_sampler_format_supported(screen, format)) {
+		retval |= PIPE_BIND_SAMPLER_VIEW;
+	}
+
+	if ((usage & (PIPE_BIND_RENDER_TARGET |
+		      PIPE_BIND_DISPLAY_TARGET |
+		      PIPE_BIND_SCANOUT |
+		      PIPE_BIND_SHARED)) &&
+	    r600_is_colorbuffer_format_supported(format)) {
+		retval |= usage &
+			  (PIPE_BIND_RENDER_TARGET |
+			   PIPE_BIND_DISPLAY_TARGET |
+			   PIPE_BIND_SCANOUT |
+			   PIPE_BIND_SHARED);
+	}
+
+	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+	    r600_is_zs_format_supported(format)) {
+		retval |= PIPE_BIND_DEPTH_STENCIL;
+	}
+
+	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+	    r600_is_vertex_format_supported(format)) {
+		retval |= PIPE_BIND_VERTEX_BUFFER;
+	}
+
+	if (usage & PIPE_BIND_TRANSFER_READ)
+		retval |= PIPE_BIND_TRANSFER_READ;
+	if (usage & PIPE_BIND_TRANSFER_WRITE)
+		retval |= PIPE_BIND_TRANSFER_WRITE;
+
+	return retval == usage;
+}
 
 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
 {
@@ -63,6 +646,7 @@ void r600_polygon_offset_update(struct r600_pipe_context *rctx)
 			offset_units *= 2.0f;
 			break;
 		case PIPE_FORMAT_Z32_FLOAT:
+		case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 			depth = -23;
 			offset_units *= 1.0f;
 			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
@@ -831,7 +1415,7 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
 	/* EXPORT_NORM is an optimzation that can be enabled for better
 	 * performance in certain cases
 	 */
-	if (rctx->family < CHIP_RV770) {
+	if (rctx->chip_class == R600) {
 		/* EXPORT_NORM can be enabled if:
 		 * - 11-bit or smaller UNORM/SNORM/SRGB
 		 * - BLEND_CLAMP is enabled
@@ -992,7 +1576,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	r600_pipe_state_add_reg(rstate,
 				R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
 				0xFFFFFFFF, NULL);
-	if (rctx->family >= CHIP_RV770) {
+	if (rctx->chip_class >= R700) {
 		r600_pipe_state_add_reg(rstate,
 					R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
 					0xFFFFFFFF, NULL);
@@ -1086,16 +1670,13 @@ void r600_init_state_functions(struct r600_pipe_context *rctx)
 
 void r600_adjust_gprs(struct r600_pipe_context *rctx)
 {
-	enum radeon_family family;
 	struct r600_pipe_state rstate;
 	unsigned num_ps_gprs = rctx->default_ps_gprs;
 	unsigned num_vs_gprs = rctx->default_vs_gprs;
 	unsigned tmp;
 	int diff;
 
-	family = r600_get_family(rctx->radeon);
-
-	if (family >= CHIP_CEDAR)
+	if (rctx->chip_class >= EVERGREEN)
 		return;
 
 	if (!rctx->ps_shader && !rctx->vs_shader)
@@ -1147,7 +1728,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
 	struct r600_pipe_state *rstate = &rctx->config;
 	u32 tmp;
 
-	family = r600_get_family(rctx->radeon);
+	family = rctx->family;
 	ps_prio = 0;
 	vs_prio = 1;
 	gs_prio = 2;
@@ -1328,7 +1909,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
 	r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
 	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
 
-	if (family >= CHIP_RV770) {
+	if (rctx->chip_class >= R700) {
 		r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
 		r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
 					S_009508_DISABLE_CUBE_ANISO(1) |
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index d9140403e5a..408eaed491b 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -109,7 +109,7 @@ void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 	rctx->states[rs->rstate.id] = &rs->rstate;
 	r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
 
-	if (rctx->family >= CHIP_CEDAR) {
+	if (rctx->chip_class >= EVERGREEN) {
 		evergreen_polygon_offset_update(rctx);
 	} else {
 		r600_polygon_offset_update(rctx);
@@ -212,7 +212,7 @@ void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 	/* Zero states. */
 	for (i = 0; i < count; i++) {
 		if (!buffers[i].buffer) {
-			if (rctx->family >= CHIP_CEDAR) {
+			if (rctx->chip_class >= EVERGREEN) {
 				evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 			} else {
 				r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
@@ -220,7 +220,7 @@ void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 		}
 	}
 	for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
-		if (rctx->family >= CHIP_CEDAR) {
+		if (rctx->chip_class >= EVERGREEN) {
 			evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
 		} else {
 			r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
@@ -367,7 +367,7 @@ static void r600_spi_update(struct r600_pipe_context *rctx)
 	for (i = 0; i < rshader->ninput; i++) {
 		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
 		    rshader->input[i].name == TGSI_SEMANTIC_FACE)
-			if (rctx->family >= CHIP_CEDAR)
+			if (rctx->chip_class >= EVERGREEN)
 				continue;
 			else
 				sid=0;
@@ -387,7 +387,7 @@ static void r600_spi_update(struct r600_pipe_context *rctx)
 			tmp |= S_028644_PT_SPRITE_TEX(1);
 		}
 
-		if (rctx->family < CHIP_CEDAR) {
+		if (rctx->chip_class < EVERGREEN) {
 			if (rshader->input[i].centroid)
 				tmp |= S_028644_SEL_CENTROID(1);
 
@@ -434,14 +434,14 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 
 		rstate = &rctx->vs_const_buffer_resource[index];
 		if (!rstate->id) {
-			if (rctx->family >= CHIP_CEDAR) {
+			if (rctx->chip_class >= EVERGREEN) {
 				evergreen_pipe_init_buffer_resource(rctx, rstate);
 			} else {
 				r600_pipe_init_buffer_resource(rctx, rstate);
 			}
 		}
 
-		if (rctx->family >= CHIP_CEDAR) {
+		if (rctx->chip_class >= EVERGREEN) {
 			evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
 			evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
 		} else {
@@ -462,13 +462,13 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 
 		rstate = &rctx->ps_const_buffer_resource[index];
 		if (!rstate->id) {
-			if (rctx->family >= CHIP_CEDAR) {
+			if (rctx->chip_class >= EVERGREEN) {
 				evergreen_pipe_init_buffer_resource(rctx, rstate);
 			} else {
 				r600_pipe_init_buffer_resource(rctx, rstate);
 			}
 		}
-		if (rctx->family >= CHIP_CEDAR) {
+		if (rctx->chip_class >= EVERGREEN) {
 			evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
 			evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
 		} else {
@@ -521,14 +521,14 @@ static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
 		offset += vertex_buffer->buffer_offset + r600_bo_offset(rbuffer->bo);
 
 		if (!rstate->id) {
-			if (rctx->family >= CHIP_CEDAR) {
+			if (rctx->chip_class >= EVERGREEN) {
 				evergreen_pipe_init_buffer_resource(rctx, rstate);
 			} else {
 				r600_pipe_init_buffer_resource(rctx, rstate);
 			}
 		}
 
-		if (rctx->family >= CHIP_CEDAR) {
+		if (rctx->chip_class >= EVERGREEN) {
 			evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride);
 			evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
 		} else {
@@ -600,7 +600,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		r600_shader_rebuild(ctx, rctx->vs_shader);
 
 	if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
-	    ((rctx->family >= CHIP_CEDAR) && rctx->ps_shader->shader.fs_write_all &&
+	    ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 	     (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)))
 		r600_shader_rebuild(ctx, rctx->ps_shader);
 
@@ -655,7 +655,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		rdraw.indices_bo_offset = draw.index_buffer_offset;
 	}
 
-	if (rctx->family >= CHIP_CEDAR) {
+	if (rctx->chip_class >= EVERGREEN) {
 		evergreen_context_draw(&rctx->ctx, &rdraw);
 	} else {
 		r600_context_draw(&rctx->ctx, &rdraw);
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
deleted file mode 100644
index 8711dbf1720..00000000000
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ /dev/null
@@ -1,614 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef R600_STATE_INLINES_H
-#define R600_STATE_INLINES_H
-
-#include "util/u_format.h"
-#include "r600d.h"
-#include "r600_formats.h"
-
-static INLINE uint32_t r600_translate_blend_function(int blend_func)
-{
-	switch (blend_func) {
-	case PIPE_BLEND_ADD:
-		return V_028804_COMB_DST_PLUS_SRC;
-	case PIPE_BLEND_SUBTRACT:
-		return V_028804_COMB_SRC_MINUS_DST;
-	case PIPE_BLEND_REVERSE_SUBTRACT:
-		return V_028804_COMB_DST_MINUS_SRC;
-	case PIPE_BLEND_MIN:
-		return V_028804_COMB_MIN_DST_SRC;
-	case PIPE_BLEND_MAX:
-		return V_028804_COMB_MAX_DST_SRC;
-	default:
-		R600_ERR("Unknown blend function %d\n", blend_func);
-		assert(0);
-		break;
-	}
-	return 0;
-}
-
-static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
-{
-	switch (blend_fact) {
-	case PIPE_BLENDFACTOR_ONE:
-		return V_028804_BLEND_ONE;
-	case PIPE_BLENDFACTOR_SRC_COLOR:
-		return V_028804_BLEND_SRC_COLOR;
-	case PIPE_BLENDFACTOR_SRC_ALPHA:
-		return V_028804_BLEND_SRC_ALPHA;
-	case PIPE_BLENDFACTOR_DST_ALPHA:
-		return V_028804_BLEND_DST_ALPHA;
-	case PIPE_BLENDFACTOR_DST_COLOR:
-		return V_028804_BLEND_DST_COLOR;
-	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
-		return V_028804_BLEND_SRC_ALPHA_SATURATE;
-	case PIPE_BLENDFACTOR_CONST_COLOR:
-		return V_028804_BLEND_CONST_COLOR;
-	case PIPE_BLENDFACTOR_CONST_ALPHA:
-		return V_028804_BLEND_CONST_ALPHA;
-	case PIPE_BLENDFACTOR_ZERO:
-		return V_028804_BLEND_ZERO;
-	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
-		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
-	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
-		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
-	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
-		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
-	case PIPE_BLENDFACTOR_INV_DST_COLOR:
-		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
-	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
-		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
-	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
-		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
-	case PIPE_BLENDFACTOR_SRC1_COLOR:
-		return V_028804_BLEND_SRC1_COLOR;
-	case PIPE_BLENDFACTOR_SRC1_ALPHA:
-		return V_028804_BLEND_SRC1_ALPHA;
-	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
-		return V_028804_BLEND_INV_SRC1_COLOR;
-	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
-		return V_028804_BLEND_INV_SRC1_ALPHA;
-	default:
-		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
-		assert(0);
-		break;
-	}
-	return 0;
-}
-
-static INLINE uint32_t r600_translate_stencil_op(int s_op)
-{
-	switch (s_op) {
-	case PIPE_STENCIL_OP_KEEP:
-		return V_028800_STENCIL_KEEP;
-	case PIPE_STENCIL_OP_ZERO:
-		return V_028800_STENCIL_ZERO;
-	case PIPE_STENCIL_OP_REPLACE:
-		return V_028800_STENCIL_REPLACE;
-	case PIPE_STENCIL_OP_INCR:
-		return V_028800_STENCIL_INCR;
-	case PIPE_STENCIL_OP_DECR:
-		return V_028800_STENCIL_DECR;
-	case PIPE_STENCIL_OP_INCR_WRAP:
-		return V_028800_STENCIL_INCR_WRAP;
-	case PIPE_STENCIL_OP_DECR_WRAP:
-		return V_028800_STENCIL_DECR_WRAP;
-	case PIPE_STENCIL_OP_INVERT:
-		return V_028800_STENCIL_INVERT;
-	default:
-		R600_ERR("Unknown stencil op %d", s_op);
-		assert(0);
-		break;
-	}
-	return 0;
-}
-
-static INLINE uint32_t r600_translate_fill(uint32_t func)
-{
-	switch(func) {
-	case PIPE_POLYGON_MODE_FILL:
-		return 2;
-	case PIPE_POLYGON_MODE_LINE:
-		return 1;
-	case PIPE_POLYGON_MODE_POINT:
-		return 0;
-	default:
-		assert(0);
-		return 0;
-	}
-}
-
-/* translates straight */
-static INLINE uint32_t r600_translate_ds_func(int func)
-{
-	return func;
-}
-
-static inline unsigned r600_tex_wrap(unsigned wrap)
-{
-	switch (wrap) {
-	default:
-	case PIPE_TEX_WRAP_REPEAT:
-		return V_03C000_SQ_TEX_WRAP;
-	case PIPE_TEX_WRAP_CLAMP:
-		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
-	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
-		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
-	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
-		return V_03C000_SQ_TEX_CLAMP_BORDER;
-	case PIPE_TEX_WRAP_MIRROR_REPEAT:
-		return V_03C000_SQ_TEX_MIRROR;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
-	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
-		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
-	}
-}
-
-static inline unsigned r600_tex_filter(unsigned filter)
-{
-	switch (filter) {
-	default:
-	case PIPE_TEX_FILTER_NEAREST:
-		return V_03C000_SQ_TEX_XY_FILTER_POINT;
-	case PIPE_TEX_FILTER_LINEAR:
-		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
-	}
-}
-
-static inline unsigned r600_tex_mipfilter(unsigned filter)
-{
-	switch (filter) {
-	case PIPE_TEX_MIPFILTER_NEAREST:
-		return V_03C000_SQ_TEX_Z_FILTER_POINT;
-	case PIPE_TEX_MIPFILTER_LINEAR:
-		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
-	default:
-	case PIPE_TEX_MIPFILTER_NONE:
-		return V_03C000_SQ_TEX_Z_FILTER_NONE;
-	}
-}
-
-static inline unsigned r600_tex_compare(unsigned compare)
-{
-	switch (compare) {
-	default:
-	case PIPE_FUNC_NEVER:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
-	case PIPE_FUNC_LESS:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
-	case PIPE_FUNC_EQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
-	case PIPE_FUNC_LEQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
-	case PIPE_FUNC_GREATER:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
-	case PIPE_FUNC_NOTEQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
-	case PIPE_FUNC_GEQUAL:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
-	case PIPE_FUNC_ALWAYS:
-		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
-	}
-}
-
-static inline unsigned r600_tex_swizzle(unsigned swizzle)
-{
-	switch (swizzle) {
-	case PIPE_SWIZZLE_RED:
-		return V_038010_SQ_SEL_X;
-	case PIPE_SWIZZLE_GREEN:
-		return V_038010_SQ_SEL_Y;
-	case PIPE_SWIZZLE_BLUE:
-		return V_038010_SQ_SEL_Z;
-	case PIPE_SWIZZLE_ALPHA:
-		return V_038010_SQ_SEL_W;
-	case PIPE_SWIZZLE_ZERO:
-		return V_038010_SQ_SEL_0;
-	default:
-	case PIPE_SWIZZLE_ONE:
-		return V_038010_SQ_SEL_1;
-	}
-}
-
-static inline unsigned r600_format_type(unsigned format_type)
-{
-	switch (format_type) {
-	default:
-	case UTIL_FORMAT_TYPE_UNSIGNED:
-		return V_038010_SQ_FORMAT_COMP_UNSIGNED;
-	case UTIL_FORMAT_TYPE_SIGNED:
-		return V_038010_SQ_FORMAT_COMP_SIGNED;
-	case UTIL_FORMAT_TYPE_FIXED:
-		return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
-	}
-}
-
-static inline unsigned r600_tex_dim(unsigned dim)
-{
-	switch (dim) {
-	default:
-	case PIPE_TEXTURE_1D:
-		return V_038000_SQ_TEX_DIM_1D;
-	case PIPE_TEXTURE_1D_ARRAY:
-		return V_038000_SQ_TEX_DIM_1D_ARRAY;
-	case PIPE_TEXTURE_2D:
-	case PIPE_TEXTURE_RECT:
-		return V_038000_SQ_TEX_DIM_2D;
-	case PIPE_TEXTURE_2D_ARRAY:
-		return V_038000_SQ_TEX_DIM_2D_ARRAY;
-	case PIPE_TEXTURE_3D:
-		return V_038000_SQ_TEX_DIM_3D;
-	case PIPE_TEXTURE_CUBE:
-		return V_038000_SQ_TEX_DIM_CUBEMAP;
-	}
-}
-
-static inline uint32_t r600_translate_dbformat(enum pipe_format format)
-{
-	switch (format) {
-	case PIPE_FORMAT_Z16_UNORM:
-		return V_028010_DEPTH_16;
-	case PIPE_FORMAT_Z24X8_UNORM:
-		return V_028010_DEPTH_X8_24;
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return V_028010_DEPTH_8_24;
-	default:
-		return ~0;
-	}
-}
-
-static inline uint32_t r600_translate_colorswap(enum pipe_format format)
-{
-	switch (format) {
-	/* 8-bit buffers. */
-	case PIPE_FORMAT_A8_UNORM:
-		return V_0280A0_SWAP_ALT_REV;
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_L8_SRGB:
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R8_SNORM:
-		return V_0280A0_SWAP_STD;
-
-	case PIPE_FORMAT_L4A4_UNORM:
-		return V_0280A0_SWAP_ALT;
-
-	/* 16-bit buffers. */
-	case PIPE_FORMAT_B5G6R5_UNORM:
-		return V_0280A0_SWAP_STD_REV;
-
-	case PIPE_FORMAT_B5G5R5A1_UNORM:
-	case PIPE_FORMAT_B5G5R5X1_UNORM:
-		return V_0280A0_SWAP_ALT;
-
-	case PIPE_FORMAT_B4G4R4A4_UNORM:
-	case PIPE_FORMAT_B4G4R4X4_UNORM:
-		return V_0280A0_SWAP_ALT;
-
-	case PIPE_FORMAT_Z16_UNORM:
-		return V_0280A0_SWAP_STD;
-
-	case PIPE_FORMAT_L8A8_UNORM:
-	case PIPE_FORMAT_L8A8_SRGB:
-		return V_0280A0_SWAP_ALT;
-	case PIPE_FORMAT_R8G8_UNORM:
-		return V_0280A0_SWAP_STD;
-
-	case PIPE_FORMAT_R16_UNORM:
-	case PIPE_FORMAT_R16_SNORM:
-	case PIPE_FORMAT_R16_FLOAT:
-		return V_0280A0_SWAP_STD;
-
-	/* 32-bit buffers. */
-
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-		return V_0280A0_SWAP_STD_REV;
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
-		return V_0280A0_SWAP_ALT;
-
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-		return V_0280A0_SWAP_ALT;
-
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-		return V_0280A0_SWAP_ALT_REV;
-	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-		return V_0280A0_SWAP_STD;
-
-	case PIPE_FORMAT_A8B8G8R8_UNORM:
-	case PIPE_FORMAT_X8B8G8R8_UNORM:
-	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
-		return V_0280A0_SWAP_STD_REV;
-
-	case PIPE_FORMAT_Z24X8_UNORM:
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return V_0280A0_SWAP_STD;
-
-	case PIPE_FORMAT_X8Z24_UNORM:
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-		return V_0280A0_SWAP_STD;
-
-	case PIPE_FORMAT_R10G10B10A2_UNORM:
-	case PIPE_FORMAT_R10G10B10X2_SNORM:
-	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
-		return V_0280A0_SWAP_STD;
-
-	case PIPE_FORMAT_B10G10R10A2_UNORM:
-		return V_0280A0_SWAP_ALT;
-
-	case PIPE_FORMAT_R11G11B10_FLOAT:
-	case PIPE_FORMAT_R16G16_UNORM:
-	case PIPE_FORMAT_R16G16_FLOAT:
-	case PIPE_FORMAT_R32_FLOAT:
-		return V_0280A0_SWAP_STD;
-
-	/* 64-bit buffers. */
-	case PIPE_FORMAT_R32G32_FLOAT:
-	case PIPE_FORMAT_R16G16B16A16_UNORM:
-	case PIPE_FORMAT_R16G16B16A16_SNORM:
-	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-
-	/* 128-bit buffers. */
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-	case PIPE_FORMAT_R32G32B32A32_SNORM:
-	case PIPE_FORMAT_R32G32B32A32_UNORM:
-		return V_0280A0_SWAP_STD;
-	default:
-		R600_ERR("unsupported colorswap format %d\n", format);
-		return ~0;
-	}
-	return ~0;
-}
-
-static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
-{
-	switch (format) {
-	case PIPE_FORMAT_L4A4_UNORM:
-		return V_0280A0_COLOR_4_4;
-
-	/* 8-bit buffers. */
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_L8_SRGB:
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R8_SNORM:
-		return V_0280A0_COLOR_8;
-
-	/* 16-bit buffers. */
-	case PIPE_FORMAT_B5G6R5_UNORM:
-		return V_0280A0_COLOR_5_6_5;
-
-	case PIPE_FORMAT_B5G5R5A1_UNORM:
-	case PIPE_FORMAT_B5G5R5X1_UNORM:
-		return V_0280A0_COLOR_1_5_5_5;
-
-	case PIPE_FORMAT_B4G4R4A4_UNORM:
-	case PIPE_FORMAT_B4G4R4X4_UNORM:
-		return V_0280A0_COLOR_4_4_4_4;
-
-	case PIPE_FORMAT_Z16_UNORM:
-		return V_0280A0_COLOR_16;
-
-	case PIPE_FORMAT_L8A8_UNORM:
-	case PIPE_FORMAT_L8A8_SRGB:
-	case PIPE_FORMAT_R8G8_UNORM:
-		return V_0280A0_COLOR_8_8;
-
-	case PIPE_FORMAT_R16_UNORM:
-	case PIPE_FORMAT_R16_SNORM:
-		return V_0280A0_COLOR_16;
-
-	case PIPE_FORMAT_R16_FLOAT:
-		return V_0280A0_COLOR_16_FLOAT;
-
-	/* 32-bit buffers. */
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-	case PIPE_FORMAT_A8B8G8R8_UNORM:
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
-	case PIPE_FORMAT_X8B8G8R8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_R8G8B8_UNORM:
-		return V_0280A0_COLOR_8_8_8_8;
-
-	case PIPE_FORMAT_R10G10B10A2_UNORM:
-	case PIPE_FORMAT_R10G10B10X2_SNORM:
-	case PIPE_FORMAT_B10G10R10A2_UNORM:
-	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
-		return V_0280A0_COLOR_2_10_10_10;
-
-	case PIPE_FORMAT_Z24X8_UNORM:
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return V_0280A0_COLOR_8_24;
-
-	case PIPE_FORMAT_X8Z24_UNORM:
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-		return V_0280A0_COLOR_24_8;
-
-	case PIPE_FORMAT_R32_FLOAT:
-		return V_0280A0_COLOR_32_FLOAT;
-
-	case PIPE_FORMAT_R16G16_FLOAT:
-		return V_0280A0_COLOR_16_16_FLOAT;
-
-	case PIPE_FORMAT_R16G16_SSCALED:
-	case PIPE_FORMAT_R16G16_UNORM:
-		return V_0280A0_COLOR_16_16;
-
-	case PIPE_FORMAT_R11G11B10_FLOAT:
-		return V_0280A0_COLOR_10_11_11_FLOAT;
-
-	/* 64-bit buffers. */
-	case PIPE_FORMAT_R16G16B16_USCALED:
-	case PIPE_FORMAT_R16G16B16A16_USCALED:
-	case PIPE_FORMAT_R16G16B16_SSCALED:
-	case PIPE_FORMAT_R16G16B16A16_SSCALED:
-	case PIPE_FORMAT_R16G16B16A16_UNORM:
-	case PIPE_FORMAT_R16G16B16A16_SNORM:
-		return V_0280A0_COLOR_16_16_16_16;
-
-	case PIPE_FORMAT_R16G16B16_FLOAT:
-	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-		return V_0280A0_COLOR_16_16_16_16_FLOAT;
-
-	case PIPE_FORMAT_R32G32_FLOAT:
-		return V_0280A0_COLOR_32_32_FLOAT;
-
-	case PIPE_FORMAT_R32G32_USCALED:
-	case PIPE_FORMAT_R32G32_SSCALED:
-		return V_0280A0_COLOR_32_32;
-
-	/* 96-bit buffers. */
-	case PIPE_FORMAT_R32G32B32_FLOAT:
-	  	return V_0280A0_COLOR_32_32_32_FLOAT;
-
-	/* 128-bit buffers. */
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-		return V_0280A0_COLOR_32_32_32_32_FLOAT;
-	case PIPE_FORMAT_R32G32B32A32_SNORM:
-	case PIPE_FORMAT_R32G32B32A32_UNORM:
-		return V_0280A0_COLOR_32_32_32_32;
-
-	/* YUV buffers. */
-	case PIPE_FORMAT_UYVY:
-	case PIPE_FORMAT_YUYV:
-	default:
-		return ~0; /* Unsupported. */
-	}
-}
-
-static INLINE uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
-{
-	if (R600_BIG_ENDIAN) {
-		switch(colorformat) {
-		case V_0280A0_COLOR_4_4:
-			return(ENDIAN_NONE);
-
-		/* 8-bit buffers. */
-		case V_0280A0_COLOR_8:
-			return(ENDIAN_NONE);
-
-		/* 16-bit buffers. */
-		case V_0280A0_COLOR_5_6_5:
-		case V_0280A0_COLOR_1_5_5_5:
-		case V_0280A0_COLOR_4_4_4_4:
-		case V_0280A0_COLOR_16:
-		case V_0280A0_COLOR_8_8:
-			return(ENDIAN_8IN16);
-
-		/* 32-bit buffers. */
-		case V_0280A0_COLOR_8_8_8_8:
-		case V_0280A0_COLOR_2_10_10_10:
-		case V_0280A0_COLOR_8_24:
-		case V_0280A0_COLOR_24_8:
-		case V_0280A0_COLOR_32_FLOAT:
-		case V_0280A0_COLOR_16_16_FLOAT:
-		case V_0280A0_COLOR_16_16:
-			return(ENDIAN_8IN32);
-
-		/* 64-bit buffers. */
-		case V_0280A0_COLOR_16_16_16_16:
-		case V_0280A0_COLOR_16_16_16_16_FLOAT:
-			return(ENDIAN_8IN16);
-
-		case V_0280A0_COLOR_32_32_FLOAT:
-		case V_0280A0_COLOR_32_32:
-			return(ENDIAN_8IN32);
-
-		/* 128-bit buffers. */
-		case V_0280A0_COLOR_32_32_32_FLOAT:
-		case V_0280A0_COLOR_32_32_32_32_FLOAT:
-		case V_0280A0_COLOR_32_32_32_32:
-			return(ENDIAN_8IN32);
-		default:
-			return ENDIAN_NONE; /* Unsupported. */
-		}
-	} else {
-		return ENDIAN_NONE;
-	}
-}
-
-static INLINE boolean r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
-{
-	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0;
-}
-
-static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format)
-{
-	return r600_translate_colorformat(format) != ~0 &&
-	       r600_translate_colorswap(format) != ~0;
-}
-
-static INLINE boolean r600_is_zs_format_supported(enum pipe_format format)
-{
-	return r600_translate_dbformat(format) != ~0;
-}
-
-static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format,
-						      enum radeon_family family)
-{
-	unsigned i;
-	const struct util_format_description *desc = util_format_description(format);
-	if (!desc)
-		return FALSE;
-
-	/* Find the first non-VOID channel. */
-	for (i = 0; i < 4; i++) {
-		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
-			break;
-		}
-	}
-	if (i == 4)
-		return FALSE;
-
-	/* No fixed, no double. */
-	if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN ||
-	    desc->channel[i].type == UTIL_FORMAT_TYPE_FIXED ||
-	    (desc->channel[i].size == 64 &&
-	     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))
-		return FALSE;
-
-	/* No scaled/norm formats with 32 bits per channel. */
-	if (desc->channel[i].size == 32 &&
-	    (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED ||
-	     desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED))
-		return FALSE;
-
-	return TRUE;
-}
-
-#endif
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 854761d17cb..63cacbbd50c 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -35,7 +35,6 @@
 #include "pipebuffer/pb_buffer.h"
 #include "r600_pipe.h"
 #include "r600_resource.h"
-#include "r600_state_inlines.h"
 #include "r600d.h"
 #include "r600_formats.h"
 
@@ -861,6 +860,12 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
 			result = FMT_8;
 			word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
 			goto out_word4;
+		case PIPE_FORMAT_Z32_FLOAT:
+			result = FMT_32_FLOAT;
+			goto out_word4;
+		case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+			result = FMT_X24_8_32_FLOAT;
+			goto out_word4;
 		default:
 			goto out_unknown;
 		}
diff --git a/src/gallium/drivers/softpipe/sp_quad_depth_test.c b/src/gallium/drivers/softpipe/sp_quad_depth_test.c
index 89b2a91fc1f..15f3a8fd813 100644
--- a/src/gallium/drivers/softpipe/sp_quad_depth_test.c
+++ b/src/gallium/drivers/softpipe/sp_quad_depth_test.c
@@ -189,7 +189,8 @@ convert_quad_depth( struct depth_data *data,
 
 
 /**
- * Compute the depth_data::shader_stencil_refs[] values from the float fragment stencil values.
+ * Compute the depth_data::shader_stencil_refs[] values from the float
+ * fragment stencil values.
  */
 static void
 convert_quad_stencil( struct depth_data *data, 
@@ -205,10 +206,9 @@ convert_quad_stencil( struct depth_data *data,
    case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
    case PIPE_FORMAT_X8Z24_UNORM:
    case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-      {
-         for (j = 0; j < QUAD_SIZE; j++) {
-            data->shader_stencil_refs[j] = ((unsigned)(quad->output.stencil[j]));
-         }
+   case PIPE_FORMAT_S8_USCALED:
+      for (j = 0; j < QUAD_SIZE; j++) {
+         data->shader_stencil_refs[j] = ((unsigned)(quad->output.stencil[j]));
       }
       break;
    default:
@@ -216,6 +216,7 @@ convert_quad_stencil( struct depth_data *data,
    }
 }
 
+
 /**
  * Write data->bzzzz[] values and data->stencilVals into the Z/stencil buffer.
  */
diff --git a/src/gallium/state_trackers/dri/common/dri_context.c b/src/gallium/state_trackers/dri/common/dri_context.c
index 08bbdf96e34..e6612b1911d 100644
--- a/src/gallium/state_trackers/dri/common/dri_context.c
+++ b/src/gallium/state_trackers/dri/common/dri_context.c
@@ -143,8 +143,6 @@ dri_unbind_context(__DRIcontext * cPriv)
    /* dri_util.c ensures cPriv is not null */
    struct dri_screen *screen = dri_screen(cPriv->driScreenPriv);
    struct dri_context *ctx = dri_context(cPriv);
-   struct dri_drawable *draw = dri_drawable(ctx->dPriv);
-   struct dri_drawable *read = dri_drawable(ctx->rPriv);
    struct st_api *stapi = screen->st_api;
 
    if (--ctx->bind_count == 0) {
diff --git a/src/gallium/state_trackers/egl/x11/x11_screen.c b/src/gallium/state_trackers/egl/x11/x11_screen.c
index f1cc4400ba5..6155b4d03c0 100644
--- a/src/gallium/state_trackers/egl/x11/x11_screen.c
+++ b/src/gallium/state_trackers/egl/x11/x11_screen.c
@@ -452,6 +452,12 @@ dri2InvalidateBuffers(Display *dpy, XID drawable)
 extern unsigned
 dri2GetSwapEventType(Display *dpy, XID drawable);
 
+extern void *
+dri2GetGlxDrawableFromXDrawableId(Display *dpy, XID id);
+
+extern void *
+GetGLXDrawable(Display *dpy, XID drawable);
+
 /**
  * This is also called from src/glx/dri2.c.
  */
@@ -460,4 +466,16 @@ unsigned dri2GetSwapEventType(Display *dpy, XID drawable)
    return 0;
 }
 
+void *
+dri2GetGlxDrawableFromXDrawableId(Display *dpy, XID id)
+{
+   return NULL;
+}
+
+void *
+GetGLXDrawable(Display *dpy, XID drawable)
+{
+   return NULL;
+}
+
 #endif /* GLX_DIRECT_RENDERING */
diff --git a/src/gallium/state_trackers/xa/xa_composite.c b/src/gallium/state_trackers/xa/xa_composite.c
index 5389af6f363..347fe0cd379 100644
--- a/src/gallium/state_trackers/xa/xa_composite.c
+++ b/src/gallium/state_trackers/xa/xa_composite.c
@@ -79,6 +79,25 @@ static const struct xa_composite_blend xa_blends[] = {
 };
 
 
+/*
+ * The alpha value stored in a luminance texture is read by the
+ * hardware as color.
+ */
+static unsigned
+xa_convert_blend_for_luminance(unsigned factor)
+{
+    switch(factor) {
+    case PIPE_BLENDFACTOR_DST_ALPHA:
+	return PIPE_BLENDFACTOR_DST_COLOR;
+    case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+	return PIPE_BLENDFACTOR_INV_DST_COLOR;
+    default:
+	break;
+    }
+    return factor;
+}
+
+
 static boolean
 blend_for_op(struct xa_composite_blend *blend,
 	     enum xa_composite_op op,
@@ -92,9 +111,15 @@ blend_for_op(struct xa_composite_blend *blend,
     boolean supported = FALSE;
 
     /*
-     * our default in case something goes wrong
+     * Temporarily disable component alpha since it appears buggy.
      */
+    if (src_pic->component_alpha ||
+	(mask_pic && mask_pic->component_alpha))
+	return FALSE;
 
+    /*
+     * our default in case something goes wrong
+     */
     *blend = xa_blends[XA_BLEND_OP_OVER];
 
     for (i = 0; i < num_blends; ++i) {
@@ -104,15 +129,20 @@ blend_for_op(struct xa_composite_blend *blend,
 	}
     }
 
+    if (!dst_pic->srf)
+	return supported;
+
+    if (dst_pic->srf->tex->format == PIPE_FORMAT_L8_UNORM) {
+	blend->rgb_src = xa_convert_blend_for_luminance(blend->rgb_src);
+	blend->rgb_dst = xa_convert_blend_for_luminance(blend->rgb_dst);
+    }
 
     /*
      * If there's no dst alpha channel, adjust the blend op so that we'll treat
      * it as always 1.
      */
 
-    if (dst_pic &&
-	xa_format_a(dst_pic->pict_format) == 0 &&
-	blend->alpha_dst) {
+    if (xa_format_a(dst_pic->pict_format) == 0 && blend->alpha_dst) {
 	if (blend->rgb_src == PIPE_BLENDFACTOR_DST_ALPHA)
 	    blend->rgb_src = PIPE_BLENDFACTOR_ONE;
 	else if (blend->rgb_src == PIPE_BLENDFACTOR_INV_DST_ALPHA)
@@ -191,13 +221,13 @@ xa_composite_check_accelerated(const struct xa_composite *comp)
 
     if (!xa_is_filter_accelerated(src_pic) ||
 	!xa_is_filter_accelerated(comp->mask)) {
-	return XA_ERR_INVAL;
+	return -XA_ERR_INVAL;
     }
 
 
     if (src_pic->src_pict) {
 	if (src_pic->src_pict->type != xa_src_pict_solid_fill)
-	    return XA_ERR_INVAL;
+	    return -XA_ERR_INVAL;
     }
 
     if (blend_for_op(&blend, comp->op, comp->src, comp->mask, comp->dst)) {
@@ -205,23 +235,24 @@ xa_composite_check_accelerated(const struct xa_composite *comp)
 	if (mask && mask->component_alpha &&
 	    xa_format_rgb(mask->pict_format)) {
 	    if (blend.alpha_src && blend.rgb_src != PIPE_BLENDFACTOR_ZERO) {
-		return XA_ERR_INVAL;
+		return -XA_ERR_INVAL;
 	    }
 	}
 
 	return XA_ERR_NONE;
     }
-    return XA_ERR_INVAL;
+    return -XA_ERR_INVAL;
 }
 
-static void
+static int
 bind_composite_blend_state(struct xa_context *ctx,
 			   const struct xa_composite *comp)
 {
     struct xa_composite_blend blend_opt;
     struct pipe_blend_state blend;
 
-    blend_for_op(&blend_opt, comp->op, comp->src, comp->mask, comp->dst);
+    if (!blend_for_op(&blend_opt, comp->op, comp->src, comp->mask, comp->dst))
+	return -XA_ERR_INVAL;
 
     memset(&blend, 0, sizeof(struct pipe_blend_state));
     blend.rt[0].blend_enable = 1;
@@ -233,11 +264,11 @@ bind_composite_blend_state(struct xa_context *ctx,
     blend.rt[0].alpha_dst_factor = blend_opt.rgb_dst;
 
     cso_set_blend(ctx->cso, &blend);
+    return XA_ERR_NONE;
 }
 
 static unsigned int
 picture_format_fixups(struct xa_picture *src_pic,
-		      struct xa_picture *dst_pic,
 		      int mask)
 {
     boolean set_alpha = FALSE;
@@ -253,22 +284,17 @@ picture_format_fixups(struct xa_picture *src_pic,
     src_hw_format = xa_surface_format(src);
     src_pic_format = src_pic->pict_format;
 
-    if (!src || src_hw_format == src_pic_format) {
-	if (src_pic_format == xa_format_a8) {
-	    if (mask)
-		return FS_MASK_LUMINANCE;
-	    else if (dst_pic->pict_format != xa_format_a8) {
-
-		/*
-		 * if both dst and src are luminance then
-		 * we don't want to swizzle the alpha (X) of the
-		 * source into W component of the dst because
-		 * it will break our destination
-		 */
-		return FS_SRC_LUMINANCE;
-	    }
-	}
-	return 0;
+    set_alpha = (xa_format_type_is_color(src_pic_format) &&
+		 xa_format_a(src_pic_format) == 0);
+
+    if (set_alpha)
+	ret |= mask ? FS_MASK_SET_ALPHA : FS_SRC_SET_ALPHA;
+
+    if (src_hw_format == src_pic_format) {
+	if (src->tex->format == PIPE_FORMAT_L8_UNORM)
+	    return ((mask) ? FS_MASK_LUMINANCE : FS_SRC_LUMINANCE);
+
+	return ret;
     }
 
     src_hw_type = xa_format_type(src_hw_format);
@@ -280,27 +306,21 @@ picture_format_fixups(struct xa_picture *src_pic,
 		 src_pic_type == xa_type_argb)));
 
     if (!swizzle && (src_hw_type != src_pic_type))
-	return 0;
+      return ret;
 
-    set_alpha = (xa_format_type_is_color(src_pic_format) &&
-		 xa_format_a(src_pic_type) == 0);
-
-    if (set_alpha)
-	ret |= mask ? FS_MASK_SET_ALPHA : FS_SRC_SET_ALPHA;
     if (swizzle)
 	ret |= mask ? FS_MASK_SWIZZLE_RGB : FS_SRC_SWIZZLE_RGB;
 
     return ret;
 }
 
-static void
+static int
 bind_shaders(struct xa_context *ctx, const struct xa_composite *comp)
 {
     unsigned vs_traits = 0, fs_traits = 0;
     struct xa_shader shader;
     struct xa_picture *src_pic = comp->src;
     struct xa_picture *mask_pic = comp->mask;
-    struct xa_picture *dst_pic = comp->dst;
 
     ctx->has_solid_color = FALSE;
 
@@ -321,7 +341,7 @@ bind_shaders(struct xa_context *ctx, const struct xa_composite *comp)
 	    vs_traits |= VS_COMPOSITE;
 	}
 
-	fs_traits |= picture_format_fixups(src_pic, dst_pic, 0);
+	fs_traits |= picture_format_fixups(src_pic, 0);
     }
 
     if (mask_pic) {
@@ -333,19 +353,25 @@ bind_shaders(struct xa_context *ctx, const struct xa_composite *comp)
 
 	if (mask_pic->component_alpha) {
 	    struct xa_composite_blend blend;
-	    blend_for_op(&blend, comp->op, src_pic, mask_pic, NULL);
+	    if (!blend_for_op(&blend, comp->op, src_pic, mask_pic, NULL))
+		return -XA_ERR_INVAL;
+
 	    if (blend.alpha_src) {
 		fs_traits |= FS_CA_SRCALPHA;
 	    } else
 		fs_traits |= FS_CA_FULL;
 	}
 
-	fs_traits |= picture_format_fixups(mask_pic, dst_pic, 1);
+	fs_traits |= picture_format_fixups(mask_pic, 1);
     }
 
+    if (ctx->dst->srf->format == PIPE_FORMAT_L8_UNORM)
+	fs_traits |= FS_DST_LUMINANCE;
+
     shader = xa_shaders_get(ctx->shaders, vs_traits, fs_traits);
     cso_set_vertex_shader_handle(ctx->cso, shader.vs);
     cso_set_fragment_shader_handle(ctx->cso, shader.fs);
+    return XA_ERR_NONE;
 }
 
 static void
@@ -433,12 +459,17 @@ xa_composite_prepare(struct xa_context *ctx,
     if (ret != XA_ERR_NONE)
 	return ret;
 
+    ctx->dst = dst_srf;
     renderer_bind_destination(ctx, dst_srf->srf,
 			      dst_srf->srf->width,
 			      dst_srf->srf->height);
 
-    bind_composite_blend_state(ctx, comp);
-    bind_shaders(ctx, comp);
+    ret = bind_composite_blend_state(ctx, comp);
+    if (ret != XA_ERR_NONE)
+	return ret;
+    ret = bind_shaders(ctx, comp);
+    if (ret != XA_ERR_NONE)
+	return ret;
     bind_samplers(ctx, comp);
 
     if (ctx->num_bound_samplers == 0 ) { /* solid fill */
diff --git a/src/gallium/state_trackers/xa/xa_context.c b/src/gallium/state_trackers/xa/xa_context.c
index 3cc25ed2071..118a390a14a 100644
--- a/src/gallium/state_trackers/xa/xa_context.c
+++ b/src/gallium/state_trackers/xa/xa_context.c
@@ -278,13 +278,16 @@ xa_solid_prepare(struct xa_context *ctx, struct xa_surface *dst,
     int width, height;
     int ret;
 
-    xa_pixel_to_float4(fg, ctx->solid_color);
-    ctx->has_solid_color = 1;
-
     ret = xa_surface_psurf_create(ctx, dst);
     if (ret != XA_ERR_NONE)
 	return ret;
 
+    if (dst->srf->format == PIPE_FORMAT_L8_UNORM)
+	xa_pixel_to_float4_a8(fg, ctx->solid_color);
+    else
+	xa_pixel_to_float4(fg, ctx->solid_color);
+    ctx->has_solid_color = 1;
+
     ctx->dst = dst;
     width = dst->srf->width;
     height = dst->srf->height;
diff --git a/src/gallium/state_trackers/xa/xa_priv.h b/src/gallium/state_trackers/xa/xa_priv.h
index 94627e1e9d0..e8f67a12276 100644
--- a/src/gallium/state_trackers/xa/xa_priv.h
+++ b/src/gallium/state_trackers/xa/xa_priv.h
@@ -135,6 +135,7 @@ enum xa_fs_traits {
     FS_MASK_SET_ALPHA = 1 << 13,
     FS_SRC_LUMINANCE = 1 << 14,
     FS_MASK_LUMINANCE = 1 << 15,
+    FS_DST_LUMINANCE = 1 << 16,
 
     FS_FILL = (FS_SOLID_FILL | FS_LINGRAD_FILL | FS_RADGRAD_FILL),
     FS_COMPONENT_ALPHA = (FS_CA_FULL | FS_CA_SRCALPHA)
@@ -172,6 +173,17 @@ xa_pixel_to_float4(uint32_t pixel, float *color)
     color[3] = ((float)a) / 255.;
 }
 
+static INLINE void
+xa_pixel_to_float4_a8(uint32_t pixel, float *color)
+{
+    uint32_t a;
+
+    a = (pixel >> 24) & 0xff;
+    color[0] = ((float)a) / 255.;
+    color[1] = ((float)a) / 255.;
+    color[2] = ((float)a) / 255.;
+    color[3] = ((float)a) / 255.;
+}
 
 /*
  * xa_tgsi.c
diff --git a/src/gallium/state_trackers/xa/xa_renderer.c b/src/gallium/state_trackers/xa/xa_renderer.c
index 559b2699da6..ef762f0ab49 100644
--- a/src/gallium/state_trackers/xa/xa_renderer.c
+++ b/src/gallium/state_trackers/xa/xa_renderer.c
@@ -418,6 +418,7 @@ renderer_copy_prepare(struct xa_context *r,
     struct pipe_context *pipe = r->pipe;
     struct pipe_screen *screen = pipe->screen;
     struct xa_shader shader;
+    uint32_t fs_traits = FS_COMPOSITE;
 
     assert(screen->is_format_supported(screen, dst_surface->format,
 				       PIPE_TEXTURE_2D, 0,
@@ -469,7 +470,12 @@ renderer_copy_prepare(struct xa_context *r,
     }
 
     /* shaders */
-    shader = xa_shaders_get(r->shaders, VS_COMPOSITE, FS_COMPOSITE);
+    if (src_texture->format == PIPE_FORMAT_L8_UNORM)
+	fs_traits |= FS_SRC_LUMINANCE;
+    if (dst_surface->format == PIPE_FORMAT_L8_UNORM)
+	fs_traits |= FS_DST_LUMINANCE;
+
+    shader = xa_shaders_get(r->shaders, VS_COMPOSITE, fs_traits);
     cso_set_vertex_shader_handle(r->cso, shader.vs);
     cso_set_fragment_shader_handle(r->cso, shader.fs);
 
diff --git a/src/gallium/state_trackers/xa/xa_tgsi.c b/src/gallium/state_trackers/xa/xa_tgsi.c
index fb6ffefd636..ed1690ed369 100644
--- a/src/gallium/state_trackers/xa/xa_tgsi.c
+++ b/src/gallium/state_trackers/xa/xa_tgsi.c
@@ -85,6 +85,7 @@ print_fs_traits(int fs_traits)
 	"FS_MASK_SET_ALPHA",	/* = 1 << 13, */
 	"FS_SRC_LUMINANCE",	/* = 1 << 14, */
 	"FS_MASK_LUMINANCE",	/* = 1 << 15, */
+	"FS_DST_LUMINANCE",     /* = 1 << 15, */
     };
     int i, k;
 
@@ -454,6 +455,7 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits)
     unsigned mask_set_alpha = (fs_traits & FS_MASK_SET_ALPHA) != 0;
     unsigned src_luminance = (fs_traits & FS_SRC_LUMINANCE) != 0;
     unsigned mask_luminance = (fs_traits & FS_MASK_LUMINANCE) != 0;
+    unsigned dst_luminance = (fs_traits & FS_DST_LUMINANCE) != 0;
 
 #if 0
     print_fs_traits(fs_traits);
@@ -508,7 +510,7 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits)
 #endif
 
     if (is_composite) {
-	if (has_mask || src_luminance)
+	if (has_mask || src_luminance || dst_luminance)
 	    src = ureg_DECL_temporary(ureg);
 	else
 	    src = out;
@@ -516,14 +518,14 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits)
 		    src_repeat_none, src_swizzle, src_set_alpha);
     } else if (is_fill) {
 	if (is_solid) {
-	    if (has_mask || src_luminance)
+	    if (has_mask || src_luminance || dst_luminance)
 		src = ureg_dst(src_input);
 	    else
 		ureg_MOV(ureg, out, src_input);
 	} else if (is_lingrad || is_radgrad) {
 	    struct ureg_src coords, const0124, matrow0, matrow1, matrow2;
 
-	    if (has_mask || src_luminance)
+	    if (has_mask || src_luminance || dst_luminance)
 		src = ureg_DECL_temporary(ureg);
 	    else
 		src = out;
@@ -550,7 +552,7 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits)
 	ureg_MOV(ureg, src, ureg_scalar(ureg_src(src), TGSI_SWIZZLE_X));
 	ureg_MOV(ureg, ureg_writemask(src, TGSI_WRITEMASK_XYZ),
 		 ureg_scalar(imm0, TGSI_SWIZZLE_X));
-	if (!has_mask)
+	if (!has_mask && !dst_luminance)
 	    ureg_MOV(ureg, out, ureg_src(src));
     }
 
@@ -559,11 +561,21 @@ create_fs(struct pipe_context *pipe, unsigned fs_traits)
 	xrender_tex(ureg, mask, mask_pos, mask_sampler, imm0,
 		    mask_repeat_none, mask_swizzle, mask_set_alpha);
 	/* src IN mask */
-	src_in_mask(ureg, out, ureg_src(src), ureg_src(mask),
+
+	src_in_mask(ureg, (dst_luminance) ? src : out, ureg_src(src),
+		    ureg_src(mask),
 		    comp_alpha_mask, mask_luminance);
+
 	ureg_release_temporary(ureg, mask);
     }
 
+    if (dst_luminance) {
+	/*
+	 * Make sure the alpha channel goes into the output L8 surface.
+	 */
+	ureg_MOV(ureg, out, ureg_scalar(ureg_src(src), TGSI_SWIZZLE_W));
+    }
+
     ureg_END(ureg);
 
     return ureg_create_shader_and_destroy(ureg, pipe);
diff --git a/src/gallium/targets/libgl-xlib/SConscript b/src/gallium/targets/libgl-xlib/SConscript
index 7d5d9bc47a9..ad8b0992e46 100644
--- a/src/gallium/targets/libgl-xlib/SConscript
+++ b/src/gallium/targets/libgl-xlib/SConscript
@@ -48,14 +48,17 @@ if False:
     env.Append(CPPDEFINES = 'GALLIUM_CELL')
     env.Prepend(LIBS = [cell])
 
-# TODO: write a wrapper function http://www.scons.org/wiki/WrapperFunctions
-libgl = env.SharedLibrary(
+# libGL.so.1.5
+libgl_1_5 = env.SharedLibrary(
     target ='GL',
     source = sources,
+    SHLIBSUFFIX = env['SHLIBSUFFIX'] + '.1.5',
 )
 
-if False:
-    # XXX: Only install this libGL.so if DRI not enabled
-    libgl = env.InstallSharedLibrary(libgl, version=(1, 5))
+# libGL.so.1
+libgl = env.subst('${SHLIBPREFIX}GL${SHLIBSUFFIX}')
+libgl_1 = libgl + '.1'
+env.Command(libgl_1, libgl_1_5, "ln -sf ${SOURCE.file} ${TARGET}")
+env.Command(libgl, libgl_1, "ln -sf ${SOURCE.file} ${TARGET}")
 
 env.Alias('libgl-xlib', libgl)
diff --git a/src/gallium/winsys/i915/drm/i915_drm_buffer.c b/src/gallium/winsys/i915/drm/i915_drm_buffer.c
index 01dd4bf062f..89d8e89e6a7 100644
--- a/src/gallium/winsys/i915/drm/i915_drm_buffer.c
+++ b/src/gallium/winsys/i915/drm/i915_drm_buffer.c
@@ -213,6 +213,15 @@ i915_drm_buffer_destroy(struct i915_winsys *iws,
    FREE(buffer);
 }
 
+static boolean
+i915_drm_buffer_is_busy(struct i915_winsys *iws,
+                        struct i915_winsys_buffer *buffer)
+{
+   struct i915_drm_buffer* i915_buffer = i915_drm_buffer(buffer);
+   return drm_intel_bo_busy(i915_buffer->bo);
+}
+
+
 void
 i915_drm_winsys_init_buffer_functions(struct i915_drm_winsys *idws)
 {
@@ -224,4 +233,5 @@ i915_drm_winsys_init_buffer_functions(struct i915_drm_winsys *idws)
    idws->base.buffer_unmap = i915_drm_buffer_unmap;
    idws->base.buffer_write = i915_drm_buffer_write;
    idws->base.buffer_destroy = i915_drm_buffer_destroy;
+   idws->base.buffer_is_busy = i915_drm_buffer_is_busy;
 }
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 4602f7f2a4b..b5a4d928bf5 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -186,7 +186,7 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
 
 static int radeon_drm_get_tiling(struct radeon *radeon)
 {
-	struct drm_radeon_info info;
+	struct drm_radeon_info info = {};
 	int r;
 	uint32_t tiling_config = 0;
 
@@ -208,8 +208,8 @@ static int radeon_drm_get_tiling(struct radeon *radeon)
 
 static int radeon_get_clock_crystal_freq(struct radeon *radeon)
 {
-	struct drm_radeon_info info;
-	uint32_t clock_crystal_freq;
+	struct drm_radeon_info info = {};
+	uint32_t clock_crystal_freq = 0;
 	int r;
 
 	info.request = RADEON_INFO_CLOCK_CRYSTAL_FREQ;
@@ -226,8 +226,8 @@ static int radeon_get_clock_crystal_freq(struct radeon *radeon)
 
 static int radeon_get_num_backends(struct radeon *radeon)
 {
-	struct drm_radeon_info info;
-	uint32_t num_backends;
+	struct drm_radeon_info info = {};
+	uint32_t num_backends = 0;
 	int r;
 
 	info.request = RADEON_INFO_NUM_BACKENDS;
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index a21beeeba3c..69f7884f823 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -1506,7 +1506,7 @@ void r600_context_flush(struct r600_context *ctx)
 	/* suspend queries */
 	r600_context_queries_suspend(ctx);
 
-	if (ctx->radeon->family >= CHIP_CEDAR)
+	if (ctx->radeon->chip_class >= EVERGREEN)
 		evergreen_context_flush_dest_caches(ctx);
 	else
 		r600_context_flush_dest_caches(ctx);
@@ -1567,7 +1567,7 @@ void r600_context_flush(struct r600_context *ctx)
 	r600_init_cs(ctx);
 
 	/* resume queries */
-	r600_context_queries_resume(ctx);
+	r600_context_queries_resume(ctx, TRUE);
 
 	/* set all valid group as dirty so they get reemited on
 	 * next draw command
@@ -1727,7 +1727,7 @@ static boolean r600_query_result(struct r600_context *ctx, struct r600_query *qu
 
 void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
 {
-	unsigned required_space;
+	unsigned required_space, required_buffer;
 	int num_backends = r600_get_num_backends(ctx->radeon);
 
 	/* query request needs 6/8 dwords for begin + 6/8 dwords for end */
@@ -1741,9 +1741,13 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
 		r600_context_flush(ctx);
 	}
 
+	required_buffer = query->num_results +
+		4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
+
 	/* if query buffer is full force a flush */
-	if (query->num_results*4 >= query->buffer_size - 16) {
-		r600_context_flush(ctx);
+	if (required_buffer*4 > query->buffer_size) {
+		if (!(query->state & R600_QUERY_STATE_FLUSHED))
+			r600_context_flush(ctx);
 		r600_query_result(ctx, query, TRUE);
 	}
 
@@ -1753,9 +1757,9 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
 		u32 *results;
 		int i;
 
-		results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_DONTBLOCK | PB_USAGE_CPU_WRITE, NULL);
+		results = r600_bo_map(ctx->radeon, query->buffer, PB_USAGE_CPU_WRITE, NULL);
 		if (results) {
-			memset(results + (query->num_results * 4), 0, ctx->max_db * 4 * 4);
+			memset(results + query->num_results, 0, ctx->max_db * 4 * 4);
 
 			for (i = num_backends; i < ctx->max_db; i++) {
 				results[(i * 4)+1] = 0x80000000;
@@ -1811,6 +1815,7 @@ void r600_query_end(struct r600_context *ctx, struct r600_query *query)
 	query->num_results += 4 * (query->type == PIPE_QUERY_OCCLUSION_COUNTER ? ctx->max_db : 1);
 	query->state ^= R600_QUERY_STATE_STARTED;
 	query->state |= R600_QUERY_STATE_ENDED;
+	query->state &= ~R600_QUERY_STATE_FLUSHED;
 	ctx->num_query_running--;
 }
 
@@ -1879,7 +1884,7 @@ boolean r600_context_query_result(struct r600_context *ctx,
 {
 	uint64_t *result = (uint64_t*)vresult;
 
-	if (query->num_results) {
+	if (query->num_results && !(query->state & R600_QUERY_STATE_FLUSHED)) {
 		r600_context_flush(ctx);
 	}
 	if (!r600_query_result(ctx, query, wait))
@@ -1904,7 +1909,7 @@ void r600_context_queries_suspend(struct r600_context *ctx)
 	}
 }
 
-void r600_context_queries_resume(struct r600_context *ctx)
+void r600_context_queries_resume(struct r600_context *ctx, boolean flushed)
 {
 	struct r600_query *query;
 
@@ -1912,6 +1917,7 @@ void r600_context_queries_resume(struct r600_context *ctx)
 		if (query->state & R600_QUERY_STATE_SUSPENDED) {
 			r600_query_begin(ctx, query);
 			query->state ^= R600_QUERY_STATE_SUSPENDED;
-		}
+		} else if (flushed && query->state==R600_QUERY_STATE_ENDED)
+			query->state |= R600_QUERY_STATE_FLUSHED;
 	}
 }
author	Christian König <[email protected]>	2011-07-11 10:48:59 +0200
committer	Christian König <[email protected]>	2011-07-11 10:48:59 +0200
commit	f919547f3785b1d8839b9fc5c00ac397e30896a1 (patch)
tree	910cd4fd7ffcd2781a303bb79395a0ee3c044c7d /src/gallium
parent	cd4f18089e44872ce9e3c04ac5e808a7204ffc49 (diff)
parent	12265d26ddc72f62de927ac24e12ab41fcd8d1c5 (diff)