diff options
| author | Nicolai Hähnle <[email protected]> | 2017-09-04 11:09:46 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <[email protected]> | 2017-09-06 09:57:08 +0200 |
| commit | 34124e412f00432ba8b3b8d16e3f2168aa596622 (patch) | |
| tree | 34d407b9b6d7bdb3fac17df0bf59b2f44f6c603c /src/gallium | |
| parent | 1e247511e54767667a0a9ac0c06f3206beb005af (diff) | |
radeonsi/gfx9: always flush DB metadata on framebuffer changes
This fixes GL45-CTS.shader_image_load_store.basic-glsl-earlyFragTests.
Cc: [email protected]
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 11 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 3 |
3 files changed, 14 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index fbf8db9a786..dde0c115dc5 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -61,9 +61,9 @@ /* Writeback & invalidate the L2 metadata cache. It can only be coupled with * a CB or DB flush. */ #define SI_CONTEXT_INV_L2_METADATA (R600_CONTEXT_PRIVATE_FLAG << 5) -/* gap */ /* Framebuffer caches. */ -#define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7) +#define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6) +#define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7) #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8) /* Engine synchronization. */ #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 5bbfbdd1ac1..7e9140b8abf 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2611,9 +2611,18 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, * individual generate_mipmap blits. * Note that lower mipmap levels aren't compressed. */ - if (sctx->generate_mipmap_for_depth) + if (sctx->generate_mipmap_for_depth) { si_make_DB_shader_coherent(sctx, 1, false, sctx->framebuffer.DB_has_shader_readable_metadata); + } else if (sctx->b.chip_class == GFX9) { + /* It appears that DB metadata "leaks" in a sequence of: + * - depth clear + * - DCC decompress for shader image writes (with DB disabled) + * - render with DEPTH_BEFORE_SHADER=1 + * Flushing DB metadata works around the problem. + */ + sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META; + } /* Take the maximum of the old and new count. If the new count is lower, * dirtying is needed to disable the unbound colorbuffers. diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 81751d2186e..7ee6cf88e88 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -912,7 +912,8 @@ void si_emit_cache_flush(struct si_context *sctx) radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); } - if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) { + if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_DB | + SI_CONTEXT_FLUSH_AND_INV_DB_META)) { /* Flush HTILE. SURFACE_SYNC will wait for idle. */ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); |