r600g: inline some of the winsys r600_get functions

8 files changed, 13 insertions, 43 deletions

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 6545bcc7c34..2c7b20ae78a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1979,7 +1979,7 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
 	r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL, 0);
 
 	/* enable dynamic GPR resource management */
-	if (r600_get_minor_version(rctx->radeon) >= 7) {
+	if (rctx->screen->info.drm_minor >= 7) {
 		/* always set temp clauses */
 		r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1,
 					S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs), 0xFFFFFFFF, NULL, 0);
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 600fae94b79..719119a1599 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -84,11 +84,6 @@ struct r600_tiling_info {
 
 enum radeon_family r600_get_family(struct radeon *rw);
 enum chip_class r600_get_family_class(struct radeon *radeon);
-unsigned r600_get_clock_crystal_freq(struct radeon *radeon);
-unsigned r600_get_minor_version(struct radeon *radeon);
-unsigned r600_get_num_backends(struct radeon *radeon);
-unsigned r600_get_num_tile_pipes(struct radeon *radeon);
-unsigned r600_get_backend_map(struct radeon *radeon);
 
 /* r600_bo.c */
 struct r600_bo;
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 7c8480772d2..28b808927eb 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -389,7 +389,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 		else
 			return 14;
 	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
-		return r600_get_minor_version(rscreen->radeon) >= 9 ?
+		return rscreen->info.drm_minor >= 9 ?
 			(family >= CHIP_CEDAR ? 16384 : 8192) : 0;
 	case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
 	case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
@@ -404,7 +404,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
 	/* Timer queries, present when the clock frequency is non zero. */
 	case PIPE_CAP_TIMER_QUERY:
-		return r600_get_clock_crystal_freq(rscreen->radeon) != 0;
+		return rscreen->info.r600_clock_crystal_freq != 0;
 
 	case PIPE_CAP_MIN_TEXEL_OFFSET:
 		return -8;
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index de1f5d05f4e..e3512f7b1a6 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -104,6 +104,6 @@ void r600_init_query_functions(struct r600_pipe_context *rctx)
 	rctx->context.end_query = r600_end_query;
 	rctx->context.get_query_result = r600_get_query_result;
 
-	if (r600_get_num_backends(rctx->screen->radeon) > 0)
+	if (rctx->screen->info.r600_num_backends > 0)
 	    rctx->context.render_condition = r600_render_condition;
 }
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 4c7c7e57414..3811c496807 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -484,7 +484,7 @@ DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE);
 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 						const struct pipe_resource *templ)
 {
-	struct radeon *radeon = ((struct r600_screen*)screen)->radeon;
+	struct r600_screen *rscreen = (struct r600_screen*)screen;
 	unsigned array_mode = 0;
 
 	if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
@@ -493,7 +493,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 			array_mode = V_038000_ARRAY_1D_TILED_THIN1;
 		}
 		else if (debug_get_option_tiling_enabled() &&
-			 r600_get_minor_version(radeon) >= 9 &&
+			 rscreen->info.drm_minor >= 9 &&
 			 permit_hardware_blit(screen, templ)) {
 			array_mode = V_038000_ARRAY_2D_TILED_THIN1;
 		}
@@ -923,7 +923,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
 
 	if (r600_enable_s3tc == -1) {
 		struct r600_screen *rscreen = (struct r600_screen *)screen;
-		if (r600_get_minor_version(rscreen->radeon) >= 9)
+		if (rscreen->info.drm_minor >= 9)
 			r600_enable_s3tc = 1;
 		else
 			r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE);
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 3417eb39192..b35812686be 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -917,7 +917,7 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 	}
 
 	/* add blocks */
-	if (r600_get_family(radeon) == CHIP_CAYMAN) 
+	if (radeon->family == CHIP_CAYMAN)
 		r = r600_context_add_block(ctx, cayman_config_reg_list,
 					   Elements(cayman_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 	else
@@ -925,7 +925,7 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon)
 					   Elements(evergreen_config_reg_list), PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET);
 	if (r)
 		goto out_err;
-	if (r600_get_family(radeon) == CHIP_CAYMAN) 
+	if (radeon->family == CHIP_CAYMAN)
 		r = r600_context_add_block(ctx, cayman_context_reg_list,
 					   Elements(cayman_context_reg_list), PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET);
 	else
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 8f1fc722f6d..33fc6b7629a 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -41,31 +41,6 @@ enum chip_class r600_get_family_class(struct radeon *radeon)
 	return radeon->chip_class;
 }
 
-unsigned r600_get_clock_crystal_freq(struct radeon *radeon)
-{
-	return radeon->info.r600_clock_crystal_freq;
-}
-
-unsigned r600_get_num_backends(struct radeon *radeon)
-{
-	return radeon->info.r600_num_backends;
-}
-
-unsigned r600_get_num_tile_pipes(struct radeon *radeon)
-{
-	return radeon->info.r600_num_tile_pipes;
-}
-
-unsigned r600_get_backend_map(struct radeon *radeon)
-{
-	return radeon->info.r600_backend_map;
-}
-
-unsigned r600_get_minor_version(struct radeon *radeon)
-{
-	return radeon->info.drm_minor;
-}
-
 static unsigned radeon_family_from_device(unsigned device)
 {
 	switch (device) {
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 5d415ae6348..848e768c38c 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -35,13 +35,13 @@ void r600_get_backend_mask(struct r600_context *ctx)
 {
 	struct r600_bo * buffer;
 	u32 * results;
-	unsigned num_backends = r600_get_num_backends(ctx->radeon);
+	unsigned num_backends = ctx->radeon->info.r600_num_backends;
 	unsigned i, mask = 0;
 
 	/* if backend_map query is supported by the kernel */
 	if (ctx->radeon->info.r600_backend_map_valid) {
-		unsigned num_tile_pipes = r600_get_num_tile_pipes(ctx->radeon);
-		unsigned backend_map = r600_get_backend_map(ctx->radeon);
+		unsigned num_tile_pipes = ctx->radeon->info.r600_num_tile_pipes;
+		unsigned backend_map = ctx->radeon->info.r600_backend_map;
 		unsigned item_width, item_mask;
 
 		if (ctx->radeon->chip_class >= EVERGREEN) {
@@ -1811,7 +1811,7 @@ boolean r600_context_query_result(struct r600_context *ctx,
 	if (!r600_query_result(ctx, query, wait))
 		return FALSE;
 	if (query->type == PIPE_QUERY_TIME_ELAPSED)
-		*result = (1000000*query->result)/r600_get_clock_crystal_freq(ctx->radeon);
+		*result = (1000000 * query->result) / ctx->radeon->info.r600_clock_crystal_freq;
 	else
 		*result = query->result;
 	query->result = 0;