nir: Drop imov/fmov in favor of one mov instruction

The difference between imov and fmov has been a constant source of
confusion in NIR for years.  No one really knows why we have two or when
to use one vs. the other.  The real reason is that they do different
things in the presence of source and destination modifiers.  However,
without modifiers (which many back-ends don't have), they are identical.
Now that we've reworked nir_lower_to_source_mods to leave one abs/neg
instruction in place rather than replacing them with imov or fmov
instructions, we don't need two different instructions at all anymore.

Reviewed-by: Kristian H. Kristensen <[email protected]>
Reviewed-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Vasily Khoruzhick <[email protected]>
Acked-by: Rob Clark <[email protected]>

7 files changed, 21 insertions, 28 deletions

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 94d863d6815..ed5fea78e00 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -833,7 +833,7 @@ ttn_move_dest_masked(nir_builder *b, nir_alu_dest dest,
    if (!(dest.write_mask & write_mask))
       return;
 
-   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_imov);
+   nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
    mov->dest = dest;
    mov->dest.write_mask &= write_mask;
    mov->src[0].src = nir_src_for_ssa(def);
@@ -904,8 +904,8 @@ ttn_dst(nir_builder *b, nir_op op, nir_alu_dest dest, nir_ssa_def **src)
 {
    ttn_move_dest_masked(b, dest, nir_imm_float(b, 1.0), TGSI_WRITEMASK_X);
    ttn_move_dest_masked(b, dest, nir_fmul(b, src[0], src[1]), TGSI_WRITEMASK_Y);
-   ttn_move_dest_masked(b, dest, nir_fmov(b, src[0]), TGSI_WRITEMASK_Z);
-   ttn_move_dest_masked(b, dest, nir_fmov(b, src[1]), TGSI_WRITEMASK_W);
+   ttn_move_dest_masked(b, dest, nir_mov(b, src[0]), TGSI_WRITEMASK_Z);
+   ttn_move_dest_masked(b, dest, nir_mov(b, src[1]), TGSI_WRITEMASK_W);
 }
 
 /* LIT - Light Coefficients
@@ -1520,7 +1520,7 @@ ttn_txq(struct ttn_compile *c, nir_alu_dest dest, nir_ssa_def **src)
 
 static const nir_op op_trans[TGSI_OPCODE_LAST] = {
    [TGSI_OPCODE_ARL] = 0,
-   [TGSI_OPCODE_MOV] = nir_op_fmov,
+   [TGSI_OPCODE_MOV] = nir_op_mov,
    [TGSI_OPCODE_LIT] = 0,
    [TGSI_OPCODE_RCP] = nir_op_frcp,
    [TGSI_OPCODE_RSQ] = nir_op_frsq,
@@ -1648,7 +1648,7 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = {
 
    /* XXX: SAMPLE opcodes */
 
-   [TGSI_OPCODE_UARL] = nir_op_imov,
+   [TGSI_OPCODE_UARL] = nir_op_mov,
    [TGSI_OPCODE_UCMP] = 0,
    [TGSI_OPCODE_IABS] = nir_op_iabs,
    [TGSI_OPCODE_ISSG] = nir_op_isign,
diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
index ddf93a637af..219ba75e59d 100644
--- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
+++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c
@@ -283,7 +283,7 @@ instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
 	} nir_ir2_opc[nir_num_opcodes+1] = {
 		[0 ... nir_num_opcodes - 1] = {-1, -1},
 
-		[nir_op_fmov] = {MAXs, MAXv},
+		[nir_op_mov] = {MAXs, MAXv},
 		[nir_op_fsign] = {-1, CNDGTEv},
 		[nir_op_fnot] = {SETEs, SETEv},
 		[nir_op_for] = {MAXs, MAXv},
@@ -315,9 +315,6 @@ instr_create_alu(struct ir2_context *ctx, nir_op opcode, unsigned ncomp)
 		[nir_op_fsin] = {SIN, -1},
 		/* no fsat, fneg, fabs since source mods deal with those */
 
-		/* some nir passes still generate nir_op_imov */
-		[nir_op_imov] = {MAXs, MAXv},
-
 		/* so we can use this function with non-nir op */
 #define ir2_op_cube nir_num_opcodes
 		[ir2_op_cube] = {-1, CUBEv},
@@ -383,7 +380,7 @@ make_src_noconst(struct ir2_context *ctx, nir_src src)
 
 	if (nir_src_as_const_value(src)) {
 		assert(src.is_ssa);
-		instr = instr_create_alu(ctx, nir_op_fmov, src.ssa->num_components);
+		instr = instr_create_alu(ctx, nir_op_mov, src.ssa->num_components);
 		instr->src[0] = make_src(ctx, src);
 		return ir2_src(instr->idx, 0, IR2_SRC_SSA);
 	}
@@ -509,24 +506,24 @@ load_input(struct ir2_context *ctx, nir_dest *dst, unsigned idx)
 		 * TODO: only components that are required by fragment shader
 		 */
 		instr = instr_create_alu_reg(ctx,
-			ctx->so->is_a20x ? nir_op_fadd : nir_op_fmov, 3, NULL);
+			ctx->so->is_a20x ? nir_op_fadd : nir_op_mov, 3, NULL);
 		instr->src[0] = ir2_src(ctx->f->inputs_count, 0, IR2_SRC_INPUT);
 		instr->src[0].abs = true;
 		/* on a20x, C64 contains the tile offset */
 		instr->src[1] = ir2_src(64, 0, IR2_SRC_CONST);
 
-		instr = instr_create_alu_reg(ctx, nir_op_fmov, 4, instr);
+		instr = instr_create_alu_reg(ctx, nir_op_mov, 4, instr);
 		instr->src[0] = ir2_src(ctx->f->fragcoord, 0, IR2_SRC_INPUT);
 
 		instr = instr_create_alu_reg(ctx, nir_op_frcp, 8, instr);
 		instr->src[0] = ir2_src(ctx->f->fragcoord, IR2_SWIZZLE_Y, IR2_SRC_INPUT);
 
 		unsigned reg_idx = instr->reg - ctx->reg; /* XXX */
-		instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
+		instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
 		instr->src[0] = ir2_src(reg_idx, 0, IR2_SRC_REG);
 		break;
 	default:
-		instr = instr_create_alu_dest(ctx, nir_op_fmov, dst);
+		instr = instr_create_alu_dest(ctx, nir_op_mov, dst);
 		instr->src[0] = ir2_src(idx, 0, IR2_SRC_INPUT);
 		break;
 	}
@@ -576,7 +573,7 @@ store_output(struct ir2_context *ctx, nir_src src, unsigned slot, unsigned ncomp
 		return;
 	}
 
-	instr = instr_create_alu(ctx, nir_op_fmov, ncomp);
+	instr = instr_create_alu(ctx, nir_op_mov, ncomp);
 	instr->src[0] = make_src(ctx, src);
 	instr->alu.export = idx;
 }
@@ -600,7 +597,7 @@ emit_intrinsic(struct ir2_context *ctx, nir_intrinsic_instr *intr)
 		assert(const_offset); /* TODO can be false in ES2? */
 		idx = nir_intrinsic_base(intr);
 		idx += (uint32_t) nir_src_as_const_value(intr->src[0])[0].f32;
-		instr = instr_create_alu_dest(ctx, nir_op_fmov, &intr->dest);
+		instr = instr_create_alu_dest(ctx, nir_op_mov, &intr->dest);
 		instr->src[0] = ir2_src(idx, 0, IR2_SRC_CONST);
 		break;
 	case nir_intrinsic_discard:
@@ -780,7 +777,7 @@ emit_undef(struct ir2_context *ctx, nir_ssa_undef_instr * undef)
 
 	struct ir2_instr *instr;
 
-	instr = instr_create_alu_dest(ctx, nir_op_fmov,
+	instr = instr_create_alu_dest(ctx, nir_op_mov,
 		&(nir_dest) {.ssa = undef->def,.is_ssa = true});
 	instr->src[0] = ir2_src(0, 0, IR2_SRC_CONST);
 }
@@ -843,11 +840,11 @@ extra_position_exports(struct ir2_context *ctx, bool binning)
 
 	/* fragcoord z/w */
 	if (ctx->f->fragcoord >= 0 && !binning) {
-		instr = instr_create_alu(ctx, nir_op_fmov, 1);
+		instr = instr_create_alu(ctx, nir_op_mov, 1);
 		instr->src[0] = ir2_src(wincoord->idx, IR2_SWIZZLE_Z, IR2_SRC_SSA);
 		instr->alu.export = ctx->f->fragcoord;
 
-		instr = instr_create_alu(ctx, nir_op_fmov, 1);
+		instr = instr_create_alu(ctx, nir_op_mov, 1);
 		instr->src[0] = ctx->position;
 		instr->src[0].swizzle = IR2_SWIZZLE_W;
 		instr->alu.export = ctx->f->fragcoord;
diff --git a/src/gallium/drivers/lima/ir/gp/nir.c b/src/gallium/drivers/lima/ir/gp/nir.c
index dcfbc450091..49010d3c255 100644
--- a/src/gallium/drivers/lima/ir/gp/nir.c
+++ b/src/gallium/drivers/lima/ir/gp/nir.c
@@ -129,7 +129,7 @@ static int nir_to_gpir_opcodes[nir_num_opcodes] = {
    [nir_op_fand] = gpir_op_min,
    [nir_op_for] = gpir_op_max,
    [nir_op_fabs] = gpir_op_abs,
-   [nir_op_fmov] = gpir_op_mov,
+   [nir_op_mov] = gpir_op_mov,
 };
 
 static bool gpir_emit_alu(gpir_block *block, nir_instr *ni)
diff --git a/src/gallium/drivers/lima/ir/pp/nir.c b/src/gallium/drivers/lima/ir/pp/nir.c
index bb5038541ea..1d390827b07 100644
--- a/src/gallium/drivers/lima/ir/pp/nir.c
+++ b/src/gallium/drivers/lima/ir/pp/nir.c
@@ -117,8 +117,7 @@ static int nir_to_ppir_opcodes[nir_num_opcodes] = {
    /* not supported */
    [0 ... nir_last_opcode] = -1,
 
-   [nir_op_fmov] = ppir_op_mov,
-   [nir_op_imov] = ppir_op_mov,
+   [nir_op_mov] = ppir_op_mov,
    [nir_op_fmul] = ppir_op_mul,
    [nir_op_fadd] = ppir_op_add,
    [nir_op_fdot2] = ppir_op_dot2,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 9054060453b..a9089ea7b59 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -2845,8 +2845,7 @@ Converter::visit(nir_alu_instr *insn)
    // those are weird ALU ops and need special handling, because
    //   1. they are always componend based
    //   2. they basically just merge multiple values into one data type
-   case nir_op_imov:
-   case nir_op_fmov:
+   case nir_op_mov:
       if (!insn->dest.dest.is_ssa && insn->dest.dest.reg.reg->num_array_elems) {
          nir_reg_dest& reg = insn->dest.dest.reg;
          uint32_t goffset = regToLmemOffset[reg.reg->index];
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 640e4a5fb86..d8d37513b8b 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -786,7 +786,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
                 ALU_CASE(imax, imax);
                 ALU_CASE(umin, umin);
                 ALU_CASE(umax, umax);
-                ALU_CASE(fmov, fmov);
                 ALU_CASE(ffloor, ffloor);
                 ALU_CASE(fround_even, froundeven);
                 ALU_CASE(ftrunc, ftrunc);
@@ -797,7 +796,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
                 ALU_CASE(isub, isub);
                 ALU_CASE(imul, imul);
                 ALU_CASE(iabs, iabs);
-                ALU_CASE(imov, imov);
+                ALU_CASE(mov, imov);
 
                 ALU_CASE(feq32, feq);
                 ALU_CASE(fne32, fne);
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index ca94619826f..ecfdbac2f7c 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1128,8 +1128,7 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
         struct qreg result;
 
         switch (instr->op) {
-        case nir_op_fmov:
-        case nir_op_imov:
+        case nir_op_mov:
                 result = qir_MOV(c, src[0]);
                 break;
         case nir_op_fmul: