winsys/amdgpu: read NUM_BANKS from buffer metadata

Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>

3 files changed, 3 insertions, 21 deletions

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 41bc48a5f7e..48410785f22 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1036,6 +1036,7 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
 	surface.tile_split = metadata.tile_split;
 	surface.stencil_tile_split = metadata.stencil_tile_split;
 	surface.mtilea = metadata.mtilea;
+	surface.num_banks = metadata.num_banks;
 
 	if (metadata.macrotile == RADEON_LAYOUT_TILED)
 		array_mode = RADEON_SURF_MODE_2D;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 691d9c2f53b..4ab85ff0721 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -412,6 +412,7 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
    md->bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
    md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
    md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
+   md->num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
    md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
 
    md->size_metadata = info.metadata.size_metadata;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 13c1c3eefc8..0523f111d4e 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -108,26 +108,6 @@ static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInpu
    return ADDR_OK;
 }
 
-/**
- * This returns the number of banks for the surface.
- * Possible values: 2, 4, 8, 16.
- */
-static uint32_t cik_num_banks(struct amdgpu_winsys *ws,
-                              struct radeon_surf *surf)
-{
-   unsigned index, tileb;
-
-   tileb = 8 * 8 * surf->bpe;
-   tileb = MIN2(surf->tile_split, tileb);
-
-   for (index = 0; tileb > 64; index++) {
-      tileb >>= 1;
-   }
-   assert(index < 16);
-
-   return 2 << ((ws->amdinfo.gb_macro_tile_mode[index] >> 6) & 0x3);
-}
-
 ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
 {
    ADDR_CREATE_INPUT addrCreateInput = {0};
@@ -375,7 +355,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
        surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
       /* If any of these parameters are incorrect, the calculation
        * will fail. */
-      AddrTileInfoIn.banks = cik_num_banks(ws, surf);
+      AddrTileInfoIn.banks = surf->num_banks;
       AddrTileInfoIn.bankWidth = surf->bankw;
       AddrTileInfoIn.bankHeight = surf->bankh;
       AddrTileInfoIn.macroAspectRatio = surf->mtilea;