diff options
| author | Rafael Antognolli <[email protected]> | 2019-11-13 14:30:57 -0800 |
|---|---|---|
| committer | Rafael Antognolli <[email protected]> | 2019-11-19 21:43:09 +0000 |
| commit | dadb6ebbd1e4575b7f8ee14dc5b9447091c2ce9e (patch) | |
| tree | 2706870a11cd301c03105a572001281194d6b5d9 /src/gallium | |
| parent | d2cf3cad917758b64f700bebe50406fc81337044 (diff) | |
intel: Add workaround for stencil state.
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Sagar Ghuge <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index da6c8926001..70c572352ab 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -5612,6 +5612,18 @@ iris_upload_dirty_render_state(struct iris_context *ice, uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4; uint32_t cso_z_size = sizeof(cso_z->packets) - clear_length; iris_batch_emit(batch, cso_z->packets, cso_z_size); + if (GEN_GEN >= 12) { + /* GEN:BUG:1408224581 + * + * Workaround: Gen12LP Astep only An additional pipe control with + * post-sync = store dword operation would be required.( w/a is to + * have an additional pipe control after the stencil state whenever + * the surface state bits of this state is changing). + */ + iris_emit_pipe_control_write(batch, "WA for stencil state", + PIPE_CONTROL_WRITE_IMMEDIATE, + batch->screen->workaround_bo, 0, 0); + } union isl_color_value clear_value = { .f32 = { 0, } }; |