diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 18:35:27 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:39:53 -0400 |
| commit | 8b58a14ef76f6d6e6c71fff2cb5c8fa6662a1882 (patch) | |
| tree | c5e0bfbad7d114c929d5f1e5530d0569b0c6bc03 /src/gallium | |
| parent | b81149e258a492ed0c81058fb535f6bfdacb36da (diff) | |
ac/gpu_info: add htile_cmask_support_1d_tiling
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_clear.c | 7 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_texture.c | 6 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 3 |
3 files changed, 7 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 23977186611..0e2d2f1013b 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -437,13 +437,10 @@ static void si_do_fast_color_clear(struct si_context *sctx, !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) continue; - /* fast color clear with 1D tiling doesn't work on old kernels and CIK */ - if (sctx->chip_class == CIK && + if (sctx->chip_class <= VI && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && - sctx->screen->info.drm_major == 2 && - sctx->screen->info.drm_minor < 38) { + !sctx->screen->info.htile_cmask_support_1d_tiling) continue; - } /* Fast clear is the most appropriate place to enable DCC for * displayable surfaces. diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 804708e0516..144516e3a5e 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -922,10 +922,8 @@ static void si_texture_get_htile_size(struct si_screen *sscreen, rtex->surface.htile_size = 0; - /* HTILE is broken with 1D tiling on old kernels and CIK. */ - if (sscreen->info.chip_class >= CIK && - rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && - sscreen->info.drm_major == 2 && sscreen->info.drm_minor < 38) + if (rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && + !sscreen->info.htile_cmask_support_1d_tiling) return; /* Overalign HTILE on P2 configs to work around GPU hangs in diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 6e3162d1cf3..21579fd9563 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -529,6 +529,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */ ws->info.ib_start_alignment = 4096; ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40; + /* HTILE is broken with 1D tiling on old kernels and CIK. */ + ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK || + ws->info.drm_minor >= 38; ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; |