diff options
| author | Ilia Mirkin <[email protected]> | 2017-05-20 03:11:12 -0400 |
|---|---|---|
| committer | Emil Velikov <[email protected]> | 2017-05-22 10:19:30 +0100 |
| commit | 4da22e2b68789d6724f2f59a235a73af4f1b8557 (patch) | |
| tree | 7acdb56de771e33aa1e8f203ff690fd0c9202cda /src/gallium | |
| parent | 88309a985a72d26c68c0e908919dd3da0076a8ab (diff) | |
nvc0/ir: SHLADD's middle source must be an immediate
The instruction encodings only allow for immediates. Don't try to
replace a zero (which is dumb to have in that op in any case) with RZ.
Signed-off-by: Ilia Mirkin <[email protected]>
Cc: [email protected]
(cherry picked from commit 82e77d4e4484b5d4f6a7b4751a17c882e6d2ad69)
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 732e1a93b42..64d743708a6 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -642,6 +642,8 @@ NVC0LegalizePostRA::replaceZero(Instruction *i) for (int s = 0; i->srcExists(s); ++s) { if (s == 2 && i->op == OP_SUCLAMP) continue; + if (s == 1 && i->op == OP_SHLADD) + continue; ImmediateValue *imm = i->getSrc(s)->asImm(); if (imm) { if (i->op == OP_SELP && s == 2) { |